* Alphabetized #includes
* Removed trailing whitespace llvm-svn: 61926
This commit is contained in:
Misha Brukman
parent
550c1c46f9
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da46748ad2
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@ -6,17 +6,17 @@
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
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// register allocator for LLVM. This allocator works by constructing a PBQP
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// problem representing the register allocation problem under consideration,
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// solving this using a PBQP solver, and mapping the solution back to a
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// register assignment. If any variables are selected for spilling then spill
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// code is inserted and the process repeated.
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// code is inserted and the process repeated.
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//
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// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
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// for register allocation. For more information on PBQP for register
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// allocation see the following papers:
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// allocation see the following papers:
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//
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// (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
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// PBQP. In Proceedings of the 7th Joint Modular Languages Conference
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@ -26,7 +26,7 @@
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// architectures. In Proceedings of the Joint Conference on Languages,
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// Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
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// NY, USA, 139-148.
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//
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//
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// Author: Lang Hames
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// Email: lhames@gmail.com
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//
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@ -36,21 +36,21 @@
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#include "PBQP.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Support/Debug.h"
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#include <memory>
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <limits>
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#include <map>
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#include <memory>
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#include <set>
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#include <vector>
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#include <limits>
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using namespace llvm;
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@ -68,7 +68,7 @@ namespace {
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public:
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static char ID;
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//! Construct a PBQP register allocator.
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PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {}
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@ -119,7 +119,7 @@ namespace {
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LiveIntervalSet vregIntervalsToAlloc,
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emptyVRegIntervals;
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//! Builds a PBQP cost vector.
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template <typename RegContainer>
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PBQPVector* buildCostVector(unsigned vReg,
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@ -170,7 +170,7 @@ namespace {
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//! \brief Given a solved PBQP problem maps this solution back to a register
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//! assignment.
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bool mapPBQPToRegAlloc(pbqp *problem);
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bool mapPBQPToRegAlloc(pbqp *problem);
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//! \brief Postprocessing before final spilling. Sets basic block "live in"
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//! variables.
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@ -209,9 +209,9 @@ PBQPVector* PBQPRegAlloc::buildCostVector(unsigned vReg,
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// No coalesce - on to the next preg.
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if (cmItr == coalesces.end())
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continue;
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// We have a coalesce - insert the benefit.
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(*v)[ai + 1] = -cmItr->second;
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// We have a coalesce - insert the benefit.
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(*v)[ai + 1] = -cmItr->second;
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}
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return v;
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@ -232,7 +232,7 @@ PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix(
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// both intervals to memory safely (the cost for each individual allocation
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// to memory is accounted for by the cost vectors for each live interval).
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PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1);
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// Assume this is a zero matrix until proven otherwise. Zero matrices occur
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// between interfering live ranges with non-overlapping register sets (e.g.
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// non-overlapping reg classes, or disjoint sets of allowed regs within the
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@ -244,9 +244,9 @@ PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix(
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// Row index. Starts at 1, since the 0th row is for the spill option, which
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// is always zero.
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unsigned ri = 1;
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unsigned ri = 1;
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// Iterate over allowed sets, insert infinities where required.
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// Iterate over allowed sets, insert infinities where required.
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for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
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a1Itr != a1End; ++a1Itr) {
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@ -321,7 +321,7 @@ PBQPMatrix* PBQPRegAlloc::buildCoalescingMatrix(
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// If the row and column represent the same register insert a beneficial
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// cost to preference this allocation - it would allow us to eliminate a
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// move instruction.
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// move instruction.
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if (reg1 == *a2Itr) {
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(*m)[ri][ci] = -cBenefit;
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isZeroMatrix = false;
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@ -348,7 +348,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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typedef MachineFunction::const_iterator MFIterator;
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typedef MachineBasicBlock::const_iterator MBBIterator;
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typedef LiveInterval::const_vni_iterator VNIIterator;
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CoalesceMap coalescesFound;
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// To find coalesces we need to iterate over the function looking for
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@ -378,7 +378,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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// If both registers are physical then we can't coalesce.
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if (srcRegIsPhysical && dstRegIsPhysical)
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continue;
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// If it's a copy that includes a virtual register but the source and
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// destination classes differ then we can't coalesce, so continue with
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// the next instruction.
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@ -408,7 +408,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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}
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// If we've made it here we have a copy with compatible register classes.
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// We can probably coalesce, but we need to consider overlap.
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// We can probably coalesce, but we need to consider overlap.
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const LiveInterval *srcLI = &lis->getInterval(srcReg),
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*dstLI = &lis->getInterval(dstReg);
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@ -421,7 +421,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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bool badDef = false;
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// Test all defs of the source range.
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for (VNIIterator
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for (VNIIterator
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vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
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vniItr != vniEnd; ++vniItr) {
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@ -436,12 +436,12 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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// If we have a bad def give up, continue to the next instruction.
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if (badDef)
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continue;
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// Otherwise test definitions of the destination range.
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for (VNIIterator
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vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
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vniItr != vniEnd; ++vniItr) {
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// We want to make sure we skip the copy instruction itself.
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if ((*vniItr)->copy == instr)
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continue;
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@ -451,7 +451,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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break;
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}
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}
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// As before a bad def we give up and continue to the next instr.
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if (badDef)
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continue;
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@ -462,7 +462,7 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
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// We're good to go with the coalesce.
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float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0;
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coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
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coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
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}
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@ -521,7 +521,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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// Iterate over vreg intervals, construct live interval <-> node number
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// mappings.
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for (LiveIntervalSet::const_iterator
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for (LiveIntervalSet::const_iterator
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itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
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itr != end; ++itr) {
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const LiveInterval *li = *itr;
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@ -545,7 +545,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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// Grab pointers to the interval and its register class.
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const LiveInterval *li = node2LI[node];
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const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
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// Start by assuming all allocable registers in the class are allowed...
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RegVector liAllowed(liRC->allocation_order_begin(*mf),
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liRC->allocation_order_end(*mf));
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@ -570,7 +570,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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// Remove the overlapping reg...
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RegVector::iterator eraseItr =
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std::find(liAllowed.begin(), liAllowed.end(), pReg);
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if (eraseItr != liAllowed.end())
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liAllowed.erase(eraseItr);
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@ -581,7 +581,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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for (; *aliasItr != 0; ++aliasItr) {
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RegVector::iterator eraseItr =
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std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
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if (eraseItr != liAllowed.end()) {
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liAllowed.erase(eraseItr);
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}
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@ -595,7 +595,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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// Set the spill cost to the interval weight, or epsilon if the
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// interval weight is zero
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PBQPNum spillCost = (li->weight != 0.0) ?
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PBQPNum spillCost = (li->weight != 0.0) ?
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li->weight : std::numeric_limits<PBQPNum>::min();
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// Build a cost vector for this interval.
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@ -626,7 +626,7 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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else if (li->overlaps(*li2)) {
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m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
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}
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if (m != 0) {
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add_pbqp_edgecosts(solver, node1, node2, m);
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delete m;
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@ -635,13 +635,13 @@ pbqp* PBQPRegAlloc::constructPBQPProblem() {
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}
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// We're done, PBQP problem constructed - return it.
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return solver;
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return solver;
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}
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void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight) {
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int stackSlot = vrm->getStackSlot(spilled->reg);
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if (stackSlot == VirtRegMap::NO_STACK_SLOT)
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if (stackSlot == VirtRegMap::NO_STACK_SLOT)
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return;
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LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot);
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@ -658,13 +658,13 @@ void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight)
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}
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bool PBQPRegAlloc::mapPBQPToRegAlloc(pbqp *problem) {
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// Set to true if we have any spills
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bool anotherRoundNeeded = false;
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// Clear the existing allocation.
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vrm->clearAllVirt();
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// Iterate over the nodes mapping the PBQP solution to a register assignment.
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for (unsigned node = 0; node < node2LI.size(); ++node) {
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unsigned virtReg = node2LI[node]->reg,
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@ -734,18 +734,18 @@ void PBQPRegAlloc::finalizeAlloc() const {
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for (LiveIntervalSet::const_iterator
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itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
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itr != end; ++itr) {
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LiveInterval *li = *itr;
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LiveInterval *li = *itr;
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unsigned physReg = li->preference;
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if (physReg == 0) {
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const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
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physReg = *liRC->allocation_order_begin(*mf);
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physReg = *liRC->allocation_order_begin(*mf);
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}
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vrm->assignVirt2Phys(li->reg, physReg);
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vrm->assignVirt2Phys(li->reg, physReg);
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}
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// Finally iterate over the basic blocks to compute and set the live-in sets.
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SmallVector<MachineBasicBlock*, 8> liveInMBBs;
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MachineBasicBlock *entryMBB = &*mf->begin();
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@ -755,7 +755,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
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const LiveInterval *li = liItr->second;
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unsigned reg = 0;
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// Get the physical register for this interval
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if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
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reg = li->reg;
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@ -771,7 +771,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
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// Iterate over the ranges of the current interval...
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for (LRIterator lrItr = li->begin(), lrEnd = li->end();
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lrItr != lrEnd; ++lrItr) {
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// Find the set of basic blocks which this range is live into...
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if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
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// And add the physreg for this interval to their live-in sets.
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@ -786,7 +786,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
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}
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}
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}
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}
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bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
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@ -807,17 +807,17 @@ bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n";
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// Allocator main loop:
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//
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//
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// * Map current regalloc problem to a PBQP problem
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// * Solve the PBQP problem
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// * Map the solution back to a register allocation
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// * Spill if necessary
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//
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//
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// This process is continued till no more spills are generated.
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// Find the vreg intervals in need of allocation.
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findVRegIntervalsToAlloc();
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// If there aren't any then we're done here.
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if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty())
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return true;
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@ -832,12 +832,12 @@ bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
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DOUT << " PBQP Regalloc round " << round << ":\n";
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pbqp *problem = constructPBQPProblem();
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solve_pbqp(problem);
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pbqpAllocComplete = mapPBQPToRegAlloc(problem);
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free_pbqp(problem);
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free_pbqp(problem);
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++round;
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}
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@ -858,7 +858,7 @@ bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
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std::auto_ptr<Spiller> spiller(createSpiller());
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spiller->runOnMachineFunction(*mf, *vrm);
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return true;
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return true;
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}
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FunctionPass* llvm::createPBQPRegisterAllocator() {
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