NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419)
llvm-svn: 350000
This commit is contained in:
Roman Lebedev
parent
c90611db06
commit
da1df56e5d
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@ -232,6 +232,64 @@ define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits)
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ret i64 %masked
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}
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; 64-bit, but with 32-bit output
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; Everything done in 64-bit, truncation happens last.
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define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_a0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w9, wzr, #0x1
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; CHECK-NEXT: lsl x9, x9, x2
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: sub w9, w9, #1 // =1
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%onebit = shl i64 1, %numlowbits
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%mask = add nsw i64 %onebit, -1
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%masked = and i64 %mask, %shifted
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%res = trunc i64 %masked to i32
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ret i32 %res
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}
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; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
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define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_a1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w9, wzr, #0x1
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; CHECK-NEXT: lsl w9, w9, w2
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: sub w9, w9, #1 // =1
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%truncshifted = trunc i64 %shifted to i32
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%onebit = shl i32 1, %numlowbits
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%mask = add nsw i32 %onebit, -1
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%masked = and i32 %mask, %truncshifted
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ret i32 %masked
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}
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; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
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; Masking is 64-bit. Then truncation.
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define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_a2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w9, wzr, #0x1
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; CHECK-NEXT: lsl w9, w9, w2
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: sub w9, w9, #1 // =1
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%onebit = shl i32 1, %numlowbits
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%mask = add nsw i32 %onebit, -1
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%zextmask = zext i32 %mask to i64
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%masked = and i64 %zextmask, %shifted
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%truncmasked = trunc i64 %masked to i32
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ret i32 %truncmasked
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}
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; ---------------------------------------------------------------------------- ;
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; Pattern b. 32-bit
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; ---------------------------------------------------------------------------- ;
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@ -659,6 +717,64 @@ define i64 @bextr64_c4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits)
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ret i64 %masked
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}
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; 64-bit, but with 32-bit output
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; Everything done in 64-bit, truncation happens last.
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define i32 @bextr64_32_c0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_c0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg x9, x2
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; CHECK-NEXT: mov x10, #-1
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: lsr x9, x10, x9
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%numhighbits = sub i64 64, %numlowbits
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%mask = lshr i64 -1, %numhighbits
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%masked = and i64 %mask, %shifted
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%res = trunc i64 %masked to i32
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ret i32 %res
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}
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; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
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define i32 @bextr64_32_c1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_c1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w9, w2
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; CHECK-NEXT: mov w10, #-1
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: lsr w9, w10, w9
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%truncshifted = trunc i64 %shifted to i32
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%masked = and i32 %mask, %truncshifted
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ret i32 %masked
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}
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; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
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; Masking is 64-bit. Then truncation.
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define i32 @bextr64_32_c2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_c2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w9, w2
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; CHECK-NEXT: mov w10, #-1
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: lsr w9, w10, w9
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; CHECK-NEXT: and w0, w9, w8
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%zextmask = zext i32 %mask to i64
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%masked = and i64 %zextmask, %shifted
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%truncmasked = trunc i64 %masked to i32
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ret i32 %truncmasked
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}
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; ---------------------------------------------------------------------------- ;
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; Pattern d. 32-bit.
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; ---------------------------------------------------------------------------- ;
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@ -809,6 +925,43 @@ define i64 @bextr64_d3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits)
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ret i64 %masked
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}
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; 64-bit, but with 32-bit output
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; Everything done in 64-bit, truncation happens last.
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define i32 @bextr64_32_d0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_d0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: neg x9, x2
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; CHECK-NEXT: lsl x8, x8, x9
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; CHECK-NEXT: lsr x0, x8, x9
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%numhighbits = sub i64 64, %numlowbits
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%highbitscleared = shl i64 %shifted, %numhighbits
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%masked = lshr i64 %highbitscleared, %numhighbits
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%res = trunc i64 %masked to i32
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ret i32 %res
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}
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; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
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define i32 @bextr64_32_d1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
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; CHECK-LABEL: bextr64_32_d1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x1
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; CHECK-NEXT: neg w9, w2
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; CHECK-NEXT: lsl w8, w8, w9
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; CHECK-NEXT: lsr w0, w8, w9
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; CHECK-NEXT: ret
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%shifted = lshr i64 %val, %numskipbits
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%truncshifted = trunc i64 %shifted to i32
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%numhighbits = sub i32 32, %numlowbits
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%highbitscleared = shl i32 %truncshifted, %numhighbits
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%masked = lshr i32 %highbitscleared, %numhighbits
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ret i32 %masked
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}
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; ---------------------------------------------------------------------------- ;
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; Constant
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; ---------------------------------------------------------------------------- ;
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