MachineInstr: Reason locally about some memory objects before going to AA.
This addresses a FIXME in MachineInstr::mayAlias. llvm-svn: 310825
This commit is contained in:
Balaram Makam
parent
718c8a6a2a
commit
d9f53414de
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@ -1663,6 +1663,7 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
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bool UseTBAA) {
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const MachineFunction *MF = getParent()->getParent();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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// If neither instruction stores to memory, they can't alias in any
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// meaningful way, even if they read from the same address.
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@ -1673,9 +1674,6 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
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if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
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return false;
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if (!AA)
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return true;
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// FIXME: Need to handle multiple memory operands to support all targets.
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if (!hasOneMemOperand() || !Other.hasOneMemOperand())
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return true;
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@ -1683,9 +1681,6 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
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MachineMemOperand *MMOa = *memoperands_begin();
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MachineMemOperand *MMOb = *Other.memoperands_begin();
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if (!MMOa->getValue() || !MMOb->getValue())
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return true;
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// The following interface to AA is fashioned after DAGCombiner::isAlias
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// and operates with MachineMemOperand offset with some important
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// assumptions:
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@ -1698,21 +1693,51 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
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// - There should never be any negative offsets here.
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//
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// FIXME: Modify API to hide this math from "user"
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// FIXME: Even before we go to AA we can reason locally about some
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// Even before we go to AA we can reason locally about some
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// memory objects. It can save compile time, and possibly catch some
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// corner cases not currently covered.
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assert((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
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assert((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
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int64_t OffsetA = MMOa->getOffset();
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int64_t OffsetB = MMOb->getOffset();
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int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
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int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
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int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
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assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
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assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
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AliasResult AAResult =
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AA->alias(MemoryLocation(MMOa->getValue(), Overlapa,
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UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
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MemoryLocation(MMOb->getValue(), Overlapb,
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int64_t MinOffset = std::min(OffsetA, OffsetB);
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int64_t WidthA = MMOa->getSize();
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int64_t WidthB = MMOb->getSize();
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const Value *ValA = MMOa->getValue();
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const Value *ValB = MMOb->getValue();
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bool SameVal = (ValA && ValB && (ValA == ValB));
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if (!SameVal) {
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const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
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const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
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if (PSVa && PSVa->isConstant(&MFI))
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return false;
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if (PSVb && PSVb->isConstant(&MFI))
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return false;
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if (PSVa && PSVb && (PSVa == PSVb))
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SameVal = true;
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}
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if (SameVal) {
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int64_t MaxOffset = std::max(OffsetA, OffsetB);
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int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
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return (MinOffset + LowWidth > MaxOffset);
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}
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if (!AA)
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return true;
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if (!ValA || !ValB)
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return true;
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int64_t Overlapa = WidthA + OffsetA - MinOffset;
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int64_t Overlapb = WidthB + OffsetB - MinOffset;
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AliasResult AAResult = AA->alias(
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MemoryLocation(ValA, Overlapa, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
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MemoryLocation(ValB, Overlapb,
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UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
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return (AAResult != NoAlias);
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@ -1531,7 +1531,7 @@ define void @merge_zr64_unalign(<2 x i64>* %p) {
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; CHECK-LABEL: merge_zr64_unalign:
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; CHECK: // %entry
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; NOSTRICTALIGN-NEXT: stp xzr, xzr, [x{{[0-9]+}}]
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; STRICTALIGN: strb wzr,
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; STRICTALIGN: strb
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; STRICTALIGN: strb
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; STRICTALIGN: strb
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; STRICTALIGN: strb
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@ -452,15 +452,15 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
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; HSA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[0:3], s33 offset:8
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; HSA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[0:3], s33 offset:12
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; HSA: buffer_store_dword [[RELOAD_VAL1]], off, s[0:3], [[SP]] offset:8
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; HSA: buffer_store_dword [[RELOAD_VAL0]], off, s[0:3], [[SP]] offset:4
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; HSA: buffer_store_dword [[RELOAD_VAL1]], off, s[0:3], [[SP]] offset:8
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; MESA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[36:39], s33 offset:8
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; MESA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[36:39], s33 offset:12
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; MESA: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:8
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; MESA: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]] offset:4
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; MESA: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:8
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; GCN-NEXT: s_swappc_b64
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; GCN-NEXT: s_sub_u32 [[SP]], [[SP]], 0x200
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@ -487,8 +487,8 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
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; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:12
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; GCN-DAG: s_add_u32 [[SP]], [[SP]], 0x200
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; GCN: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:8
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; GCN: buffer_store_dword [[RELOAD_VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:4
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; GCN: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:8
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; GCN-NEXT: s_swappc_b64
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; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:16
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; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:20
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@ -179,8 +179,8 @@ define amdgpu_kernel void @global_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)
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; GCN-NOHSA: buffer_load_dwordx2
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; GCN-HSA: flat_load_dwordx2
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_LO:T[0-9]]], {{T[0-9]\.[XYZW]}}
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}},
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9]\.[XYZW]}},
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; EGCM-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 0, #1
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@ -188,8 +188,6 @@ define amdgpu_kernel void @global_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)
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; TODO: This should use DST, but for some there are redundant MOVs
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; EGCM: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
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; EGCM: 16
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; EGCM: AND_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, literal
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; EGCM: AND_INT {{[* ]*}}[[ST_HI]].X, [[DST_HI]], literal
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define amdgpu_kernel void @global_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) {
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entry:
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%ld = load <3 x i16>, <3 x i16> addrspace(1)* %in
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@ -202,8 +200,8 @@ entry:
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; GCN-NOHSA: buffer_load_dwordx2
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; GCN-HSA: flat_load_dwordx2
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_LO:T[0-9]]], {{T[0-9]\.[XYZW]}}
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}},
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9]\.[XYZW]}},
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; EGCM-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9].[XYZW]}}, 0, #1
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@ -352,22 +352,22 @@ define amdgpu_kernel void @global_zextload_v16i8_to_v16i32(<16 x i32> addrspace(
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; EG: VTX_READ_128 [[DST:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1
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; TODO: These should use DST, but for some there are redundant MOVs
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]*.[XYZW]}}, {{.*}}, 0.0, literal
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; EG-DAG: 8
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; EG-DAG: 8
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; EG-DAG: 8
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@ -530,7 +530,6 @@ define amdgpu_kernel void @local_sextload_v64i16_to_v64i32(<64 x i32> addrspace(
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; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
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; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
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; EG-DAG: LDS_WRITE
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; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
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define amdgpu_kernel void @local_zextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* %in) #0 {
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%a = load i16, i16 addrspace(3)* %in
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%ext = zext i16 %a to i64
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@ -572,7 +571,6 @@ define amdgpu_kernel void @local_sextload_i16_to_i64(i64 addrspace(3)* %out, i16
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; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
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; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
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; EG-DAG: LDS_WRITE
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; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
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define amdgpu_kernel void @local_zextload_v1i16_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i16> addrspace(3)* %in) #0 {
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%load = load <1 x i16>, <1 x i16> addrspace(3)* %in
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%ext = zext <1 x i16> %load to <1 x i64>
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@ -1,13 +1,15 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s
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; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s --check-prefix=NOREGALLOC
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s --check-prefix=REGALLOC
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@.str = private constant [1 x i8] zeroinitializer, align 1
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define void @g() {
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entry:
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;CHECK: [sp, #8]
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;CHECK: [sp, #12]
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;CHECK: [sp]
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;NOREGALLOC: [sp, #12]
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;NOREGALLOC: [sp]
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;REGALLOC: [sp]
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;REGALLOC: [sp, #12]
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tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
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ret void
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}
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@ -124,10 +124,10 @@ define void @i56_and_or(i56* %a) {
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; BE-LABEL: i56_and_or:
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; BE: @ BB#0:
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; BE-NEXT: mov r1, r0
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; BE-NEXT: mov r3, #128
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; BE-NEXT: ldrh r2, [r1, #4]!
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; BE-NEXT: strb r3, [r1, #2]
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; BE-NEXT: ldr r12, [r0]
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; BE-NEXT: ldrh r2, [r1, #4]!
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; BE-NEXT: mov r3, #128
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; BE-NEXT: strb r3, [r1, #2]
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; BE-NEXT: lsl r2, r2, #8
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; BE-NEXT: orr r2, r2, r12, lsl #24
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; BE-NEXT: orr r2, r2, #384
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@ -118,17 +118,17 @@ define void @i56_or(i56* %a) {
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; X64: # BB#0:
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; X64-NEXT: movzwl 4(%rdi), %eax
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; X64-NEXT: movzbl 6(%rdi), %ecx
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; X64-NEXT: movl (%rdi), %edx
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; X64-NEXT: movb %cl, 6(%rdi)
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; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
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; X64-NEXT: shll $16, %ecx
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; X64-NEXT: orl %eax, %ecx
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; X64-NEXT: shlq $32, %rcx
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; X64-NEXT: orq %rcx, %rdx
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; X64-NEXT: orq $384, %rdx # imm = 0x180
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; X64-NEXT: movl %edx, (%rdi)
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; X64-NEXT: shrq $32, %rdx
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; X64-NEXT: movw %dx, 4(%rdi)
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: orq %rcx, %rax
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; X64-NEXT: orq $384, %rax # imm = 0x180
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; X64-NEXT: movl %eax, (%rdi)
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; X64-NEXT: shrq $32, %rax
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; X64-NEXT: movw %ax, 4(%rdi)
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; X64-NEXT: retq
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%aa = load i56, i56* %a, align 1
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%b = or i56 %aa, 384
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@ -150,19 +150,19 @@ define void @i56_and_or(i56* %a) {
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; X64: # BB#0:
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; X64-NEXT: movzwl 4(%rdi), %eax
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; X64-NEXT: movzbl 6(%rdi), %ecx
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; X64-NEXT: movl (%rdi), %edx
|
||||
; X64-NEXT: movb %cl, 6(%rdi)
|
||||
; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
|
||||
; X64-NEXT: shll $16, %ecx
|
||||
; X64-NEXT: orl %eax, %ecx
|
||||
; X64-NEXT: shlq $32, %rcx
|
||||
; X64-NEXT: orq %rcx, %rdx
|
||||
; X64-NEXT: orq $384, %rdx # imm = 0x180
|
||||
; X64-NEXT: movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
|
||||
; X64-NEXT: andq %rdx, %rax
|
||||
; X64-NEXT: movl %eax, (%rdi)
|
||||
; X64-NEXT: shrq $32, %rax
|
||||
; X64-NEXT: movw %ax, 4(%rdi)
|
||||
; X64-NEXT: movl (%rdi), %eax
|
||||
; X64-NEXT: orq %rcx, %rax
|
||||
; X64-NEXT: orq $384, %rax # imm = 0x180
|
||||
; X64-NEXT: movabsq $72057594037927808, %rcx # imm = 0xFFFFFFFFFFFF80
|
||||
; X64-NEXT: andq %rax, %rcx
|
||||
; X64-NEXT: movl %ecx, (%rdi)
|
||||
; X64-NEXT: shrq $32, %rcx
|
||||
; X64-NEXT: movw %cx, 4(%rdi)
|
||||
; X64-NEXT: retq
|
||||
%b = load i56, i56* %a, align 1
|
||||
%c = and i56 %b, -128
|
||||
|
|
@ -188,20 +188,20 @@ define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
|
|||
; X64-NEXT: movzbl %sil, %eax
|
||||
; X64-NEXT: movzwl 4(%rdi), %ecx
|
||||
; X64-NEXT: movzbl 6(%rdi), %edx
|
||||
; X64-NEXT: movl (%rdi), %esi
|
||||
; X64-NEXT: movb %dl, 6(%rdi)
|
||||
; X64-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def>
|
||||
; X64-NEXT: shll $16, %edx
|
||||
; X64-NEXT: orl %ecx, %edx
|
||||
; X64-NEXT: shlq $32, %rdx
|
||||
; X64-NEXT: orq %rdx, %rsi
|
||||
; X64-NEXT: movl (%rdi), %ecx
|
||||
; X64-NEXT: orq %rdx, %rcx
|
||||
; X64-NEXT: shlq $13, %rax
|
||||
; X64-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
|
||||
; X64-NEXT: andq %rsi, %rcx
|
||||
; X64-NEXT: orq %rax, %rcx
|
||||
; X64-NEXT: movl %ecx, (%rdi)
|
||||
; X64-NEXT: shrq $32, %rcx
|
||||
; X64-NEXT: movw %cx, 4(%rdi)
|
||||
; X64-NEXT: movabsq $72057594037919743, %rdx # imm = 0xFFFFFFFFFFDFFF
|
||||
; X64-NEXT: andq %rcx, %rdx
|
||||
; X64-NEXT: orq %rax, %rdx
|
||||
; X64-NEXT: movl %edx, (%rdi)
|
||||
; X64-NEXT: shrq $32, %rdx
|
||||
; X64-NEXT: movw %dx, 4(%rdi)
|
||||
; X64-NEXT: retq
|
||||
%extbit = zext i1 %bit to i56
|
||||
%b = load i56, i56* %a, align 1
|
||||
|
|
|
|||
|
|
@ -12,23 +12,23 @@
|
|||
define void @t1(i32 %argc, i8** %argv) nounwind {
|
||||
entry:
|
||||
; SSE2-Darwin-LABEL: t1:
|
||||
; SSE2-Darwin: movsd _.str+16, %xmm0
|
||||
; SSE2-Darwin: movsd %xmm0, 16(%esp)
|
||||
; SSE2-Darwin: movaps _.str, %xmm0
|
||||
; SSE2-Darwin: movaps %xmm0
|
||||
; SSE2-Darwin: movsd _.str+16, %xmm0
|
||||
; SSE2-Darwin: movsd %xmm0, 16(%esp)
|
||||
; SSE2-Darwin: movb $0, 24(%esp)
|
||||
|
||||
; SSE2-Mingw32-LABEL: t1:
|
||||
; SSE2-Mingw32: movsd _.str+16, %xmm0
|
||||
; SSE2-Mingw32: movsd %xmm0, 16(%esp)
|
||||
; SSE2-Mingw32: movaps _.str, %xmm0
|
||||
; SSE2-Mingw32: movups %xmm0
|
||||
; SSE2-Mingw32: movsd _.str+16, %xmm0
|
||||
; SSE2-Mingw32: movsd %xmm0, 16(%esp)
|
||||
; SSE2-Mingw32: movb $0, 24(%esp)
|
||||
|
||||
; SSE1-LABEL: t1:
|
||||
; SSE1: movaps _.str, %xmm0
|
||||
; SSE1: movaps %xmm0
|
||||
; SSE1: movb $0, 24(%esp)
|
||||
; SSE1: movaps %xmm0
|
||||
; SSE1: movl $0, 20(%esp)
|
||||
; SSE1: movl $0, 16(%esp)
|
||||
|
||||
|
|
|
|||
|
|
@ -25,8 +25,8 @@ define i32 @pr34088() local_unnamed_addr {
|
|||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: movaps %xmm0, (%esp)
|
||||
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
|
||||
; CHECK-NEXT: movaps %xmm1, (%esp)
|
||||
; CHECK-NEXT: movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD
|
||||
; CHECK-NEXT: movaps %xmm1, (%esp)
|
||||
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
|
||||
; CHECK-NEXT: movl %ebp, %esp
|
||||
; CHECK-NEXT: popl %ebp
|
||||
|
|
|
|||
|
|
@ -16,9 +16,9 @@ define void @update(<3 x i16>* %dst, <3 x i16>* %src, i32 %n) nounwind {
|
|||
; CHECK-NEXT: movl {{\.LCPI.*}}, %eax
|
||||
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
|
||||
; CHECK-NEXT: movw $1, {{[0-9]+}}(%esp)
|
||||
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
|
||||
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
|
||||
; CHECK-NEXT: movw $1, {{[0-9]+}}(%esp)
|
||||
; CHECK-NEXT: jmp .LBB0_1
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB0_2: # %forbody
|
||||
|
|
|
|||
Loading…
Reference in New Issue