[mips] Remove remaining use of MipsCC::intArgRegs() in favour of MipsABIInfo::GetByValArgRegs() and MipsABIInfo::GetVarArgRegs()
Summary: Depends on D6112 Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6113 llvm-svn: 221521
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@ -27,3 +27,11 @@ const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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return makeArrayRef(Mips64IntRegs);
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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llvm_unreachable("Unhandled ABI");
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}
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}
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const ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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@ -38,8 +38,12 @@ public:
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bool IsEABI() const { return ThisABI == ABI::EABI; }
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bool IsEABI() const { return ThisABI == ABI::EABI; }
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ABI GetEnumValue() const { return ThisABI; }
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ABI GetEnumValue() const { return ThisABI; }
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/// The registers to use for byval arguments.
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const ArrayRef<MCPhysReg> GetByValArgRegs() const;
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const ArrayRef<MCPhysReg> GetByValArgRegs() const;
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/// The registers to use for the variable argument list.
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const ArrayRef<MCPhysReg> GetVarArgRegs() const;
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/// Ordering of ABI's
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/// Ordering of ABI's
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/// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given
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/// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given
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/// multiple ABI options.
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/// multiple ABI options.
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@ -3628,12 +3628,6 @@ unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
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return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
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return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
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}
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}
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const ArrayRef<MCPhysReg> MipsTargetLowering::MipsCC::intArgRegs() const {
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if (Subtarget.isABI_O32())
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return makeArrayRef(O32IntRegs);
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return makeArrayRef(Mips64IntRegs);
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}
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void MipsTargetLowering::copyByValRegs(
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void MipsTargetLowering::copyByValRegs(
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SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
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SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
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const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
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const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
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@ -3646,11 +3640,11 @@ void MipsTargetLowering::copyByValRegs(
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unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
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unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
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unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
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unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
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int FrameObjOffset;
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int FrameObjOffset;
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ArrayRef<MCPhysReg> ByValArgRegs = Subtarget.getABI().GetByValArgRegs();
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if (RegAreaSize)
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if (RegAreaSize)
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FrameObjOffset =
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FrameObjOffset = (int)CC.reservedArgArea() -
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(int)CC.reservedArgArea() -
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(int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
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(int)((CC.intArgRegs().size() - FirstReg) * GPRSizeInBytes);
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else
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else
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FrameObjOffset = VA.getLocMemOffset();
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FrameObjOffset = VA.getLocMemOffset();
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@ -3668,7 +3662,7 @@ void MipsTargetLowering::copyByValRegs(
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const TargetRegisterClass *RC = getRegClassFor(RegTy);
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const TargetRegisterClass *RC = getRegClassFor(RegTy);
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for (unsigned I = 0; I < NumRegs; ++I) {
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for (unsigned I = 0; I < NumRegs; ++I) {
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unsigned ArgReg = CC.intArgRegs()[FirstReg + I];
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unsigned ArgReg = ByValArgRegs[FirstReg + I];
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unsigned VReg = addLiveIn(MF, ArgReg, RC);
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unsigned VReg = addLiveIn(MF, ArgReg, RC);
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unsigned Offset = I * GPRSizeInBytes;
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unsigned Offset = I * GPRSizeInBytes;
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SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
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SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
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@ -3696,7 +3690,7 @@ void MipsTargetLowering::passByValArg(
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unsigned NumRegs = LastReg - FirstReg;
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unsigned NumRegs = LastReg - FirstReg;
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if (NumRegs) {
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if (NumRegs) {
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const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
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const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetByValArgRegs();
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bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
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bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
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unsigned I = 0;
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unsigned I = 0;
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@ -3779,7 +3773,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
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const MipsCC &CC, SDValue Chain,
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const MipsCC &CC, SDValue Chain,
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SDLoc DL, SelectionDAG &DAG,
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SDLoc DL, SelectionDAG &DAG,
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CCState &State) const {
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CCState &State) const {
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const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
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const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetVarArgRegs();
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unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
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unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
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unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
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unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
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MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
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MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
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@ -367,9 +367,6 @@ namespace llvm {
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/// register arguments. This is 16-byte if ABI is O32.
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/// register arguments. This is 16-byte if ABI is O32.
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unsigned reservedArgArea() const;
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unsigned reservedArgArea() const;
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/// Return pointer to array of integer argument registers.
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const ArrayRef<MCPhysReg> intArgRegs() const;
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private:
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private:
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CallingConv::ID CallConv;
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CallingConv::ID CallConv;
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const MipsSubtarget &Subtarget;
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const MipsSubtarget &Subtarget;
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