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[DAGCombiner] Fix a wrong check in method SimplifyVBinOp. 

This fixes a regression intruced by r199135.

Revision 199135 tried to simplify part of the logic in method
DAGCombiner::SimplifyVBinOp introducing calls to method BuildVectorSDNode::isConstant().

However, that revision wrongly changed the check performed by method
SimplifyVBinOp to identify dag nodes that can be folded.
Before revision 199135, that method only tried to simplify vector binary operations
if both operands were build_vector of Constant/ConstantFP/Undef only.

After revision 199135, method SimplifyVBinop tried to
simplify also vector binary operations with only one constant operand.

This fixes the problem restoring the old behavior of SimplifyVBinOp.

llvm-svn: 199328
This commit is contained in:
Andrea Di Biagio 2014-01-15 19:51:32 +00:00
parent 0de92d53a1
commit d7c03ec348
2 changed files with 25 additions and 2 deletions
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4
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -10391,8 +10391,8 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
RHS.getOpcode() == ISD::BUILD_VECTOR) {
// Check if both vectors are constants. If not bail out.
if (!cast<BuildVectorSDNode>(LHS)->isConstant() &&
!cast<BuildVectorSDNode>(RHS)->isConstant())
if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
cast<BuildVectorSDNode>(RHS)->isConstant()))
return SDValue();
SmallVector<SDValue, 8> Ops;

23
llvm/test/CodeGen/X86/vbinop-simplify-bug.ll Normal file
View File

@ -0,0 +1,23 @@
; RUN: llc %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse2 -mcpu=corei7
; Revision 199135 introduced a wrong check in method
; DAGCombiner::SimplifyVBinOp in an attempt to refactor some code
; using the new method 'BuildVectorSDNode::isConstant' when possible.
;
; However the modified code in method SimplifyVBinOp now wrongly
; checks that the operands of a vector bin-op are both constants.
;
; With that wrong change, this test started failing because of a
; 'fatal error in the backend':
; Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
; 0x2e2ea00: i32 = Constant<1> [ID=4]
; 0x2e2ea00: i32 = Constant<1> [ID=4]
; 0x2e2ea00: i32 = Constant<1> [ID=4]
; 0x2e2ea00: i32 = Constant<1> [ID=4]
define <8 x i32> @reduced_test_case() {
%Shuff = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 undef, i32 7, i32 9, i32 11, i32 13, i32 15>
%B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
ret <8 x i32> %B23
}