Switch SPU calling convention (function arguments)
to a Tablegen implementation. llvm-svn: 107913
This commit is contained in:
Kalle Raiskila
parent
9870460c84
commit
d799ea52cd
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@ -34,76 +34,19 @@ def RetCC_SPU : CallingConv<[
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//===----------------------------------------------------------------------===//
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// CellSPU Argument Calling Conventions
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// (note: this isn't used, but presumably should be at some point when other
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// targets do.)
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//===----------------------------------------------------------------------===//
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/*
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def CC_SPU : CallingConv<[
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CCIfType<[i8], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i16], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[i64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[f64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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CCIfType<[v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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def CCC_SPU : CallingConv<[
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CCIfType<[i8, i16, i32, i64, i128, f32, f64,
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v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
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R12, R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, R32, R33, R34, R35, R36, R37, R38,
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R39, R40, R41, R42, R43, R44, R45, R46, R47,
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R48, R49, R50, R51, R52, R53, R54, R55, R56,
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R57, R58, R59, R60, R61, R62, R63, R64, R65,
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R66, R67, R68, R69, R70, R71, R72, R73, R74,
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R75, R76, R77, R78, R79]>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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@ -112,4 +55,3 @@ def CC_SPU : CallingConv<[
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 16>>
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]>;
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*/
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@ -1014,22 +1014,26 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>();
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const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
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const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
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unsigned ArgOffset = SPUFrameInfo::minStackSize();
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unsigned ArgRegIdx = 0;
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unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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// FIXME: allow for other calling conventions
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CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
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// Add DAG nodes to load the arguments or copy them out of registers.
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for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
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EVT ObjectVT = Ins[ArgNo].VT;
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unsigned ObjSize = ObjectVT.getSizeInBits()/8;
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SDValue ArgVal;
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CCValAssign &VA = ArgLocs[ArgNo];
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if (ArgRegIdx < NumArgRegs) {
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if (VA.isRegLoc()) {
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const TargetRegisterClass *ArgRegClass;
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switch (ObjectVT.getSimpleVT().SimpleTy) {
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@ -1068,7 +1072,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
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}
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unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
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RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
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++ArgRegIdx;
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} else {
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@ -1088,12 +1092,28 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
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// vararg handling:
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if (isVarArg) {
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// unsigned int ptr_size = PtrVT.getSizeInBits() / 8;
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// FIXME: we should be able to query the argument registers from
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// tablegen generated code.
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static const unsigned ArgRegs[] = {
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SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
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SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
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SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
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SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
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SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
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SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
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SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
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SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
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SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
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SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
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SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
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};
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// size of ArgRegs array
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unsigned NumArgRegs = 77;
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// We will spill (79-3)+1 registers to the stack
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SmallVector<SDValue, 79-3+1> MemOps;
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// Create the frame slot
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for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
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FuncInfo->setVarArgsFrameIndex(
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MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
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@ -1145,8 +1165,15 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
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unsigned NumOps = Outs.size();
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unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
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const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
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const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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// FIXME: allow for other calling conventions
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CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
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const unsigned NumArgRegs = ArgLocs.size();
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// Handy pointer type
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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@ -1166,8 +1193,9 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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// And the arguments passed on the stack
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SmallVector<SDValue, 8> MemOpChains;
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for (unsigned i = 0; i != NumOps; ++i) {
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SDValue Arg = OutVals[i];
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for (; ArgRegIdx != NumOps; ++ArgRegIdx) {
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SDValue Arg = OutVals[ArgRegIdx];
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CCValAssign &VA = ArgLocs[ArgRegIdx];
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// PtrOff will be used to store the current argument to the stack if a
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// register cannot be found for it.
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@ -1190,7 +1218,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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case MVT::v8i16:
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case MVT::v16i8:
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if (ArgRegIdx != NumArgRegs) {
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RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
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false, false, 0));
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@ -191,33 +191,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
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{
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}
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// SPU's 128-bit registers used for argument passing:
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static const unsigned SPU_ArgRegs[] = {
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SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
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SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
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SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
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SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
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SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
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SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
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SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
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SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
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SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
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SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
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SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
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};
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const unsigned *
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SPURegisterInfo::getArgRegs()
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{
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return SPU_ArgRegs;
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}
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unsigned
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SPURegisterInfo::getNumArgRegs()
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{
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return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
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}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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@ -86,15 +86,6 @@ namespace llvm {
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// New methods added:
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//------------------------------------------------------------------------
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//! Return the array of argument passing registers
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/*!
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\note The size of this array is returned by getArgRegsSize().
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*/
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static const unsigned *getArgRegs();
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//! Return the size of the argument passing register array
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static unsigned getNumArgRegs();
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//! Get DWARF debugging register number
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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