Teach the x86 backend about the register constraints of its addressing mode.

Patch by Evan Cheng llvm-svn: 24423
2005-11-19 07:01:30 +00:00 · 2005-11-19 07:01:30 +00:00 · d7102c4980
parent 252d88c68e
commit d7102c4980
1 changed files with 2 additions and 1 deletions
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@ -17,8 +17,9 @@
 //

 class X86MemOperand<ValueType Ty> : Operand<Ty> {
-  let NumMIOperands = 4;
  let PrintMethod = "printMemoryOperand";
+  let NumMIOperands = 4;
+  let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
 }
 def SSECC : Operand<i8> {
  let PrintMethod = "printSSECC";