[Hexagon] Add patterns for compares of i1 values

llvm-svn: 326220
This commit is contained in:
Krzysztof Parzyszek 2018-02-27 18:31:46 +00:00
parent 9b1996ec86
commit d70f5a0eb4
2 changed files with 31 additions and 2 deletions

View File

@ -679,8 +679,10 @@ def: Pat<(i32 (zext (i1 (seteq I32:$Rs, anyimm:$s8)))),
def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
(A4_rcmpneqi I32:$Rs, imm:$s8)>;
def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),
(C2_xor I1:$Ps, I1:$Pt)>;
def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
def: Pat<(i1 (setne I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>;
def: Pat<(i1 (seteq V4I8:$Rs, V4I8:$Rt)),
(A2_vcmpbeq (ToZext64 $Rs), (ToZext64 $Rt))>;

View File

@ -0,0 +1,27 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that this compiles successfully.
; CHECK: if (p0)
target triple = "hexagon"
define void @fred() #0 {
b0:
br label %b1
b1: ; preds = %b1, %b0
%v2 = load i32, i32* undef, align 4
%v3 = select i1 undef, i32 %v2, i32 0
%v4 = and i32 %v3, 7
%v5 = icmp eq i32 %v4, 4
%v6 = or i1 undef, %v5
%v7 = and i1 undef, %v6
%v8 = xor i1 %v7, true
%v9 = or i1 undef, %v8
br i1 %v9, label %b10, label %b1
b10: ; preds = %b1
unreachable
}
attributes #0 = { nounwind "target-cpu"="hexagonv55" }