AMD family 17h (znver1) enablement
Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
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@ -111,6 +111,7 @@ enum ProcessorTypes {
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AMDATHLON,
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AMDFAM14H,
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AMDFAM16H,
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AMDFAM17H,
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CPU_TYPE_MAX
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};
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@ -149,6 +150,7 @@ enum ProcessorSubtypes {
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AMD_BTVER2,
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AMDFAM15H_BDVER3,
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AMDFAM15H_BDVER4,
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AMDFAM17H_ZNVER1,
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CPU_SUBTYPE_MAX
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};
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@ -742,6 +744,14 @@ static void getAMDProcessorTypeAndSubtype(unsigned int Family,
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}
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*Subtype = AMD_BTVER2;
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break; // "btver2"
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case 23:
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*Type = AMDFAM17H;
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if (Features & (1 << FEATURE_ADX)) {
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*Subtype = AMDFAM17H_ZNVER1;
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break; // "znver1"
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}
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*Subtype = AMD_BTVER1;
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break;
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default:
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break; // "generic"
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}
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@ -950,6 +960,15 @@ StringRef sys::getHostCPUName() {
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default:
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return "amdfam16";
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}
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case AMDFAM17H:
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switch (Subtype) {
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case AMD_BTVER1:
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return "btver1";
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case AMDFAM17H_ZNVER1:
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return "znver1";
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default:
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return "amdfam17";
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}
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default:
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return "generic";
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}
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@ -760,6 +760,42 @@ def : Proc<"bdver4", [
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FeatureMWAITX
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]>;
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// TODO: The scheduler model falls to BTVER2 model.
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// The znver1 model has to be put in place.
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// Zen
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def: ProcessorModel<"znver1", BtVer2Model, [
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FeatureADX,
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FeatureAES,
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FeatureAVX2,
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FeatureBMI,
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FeatureBMI2,
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FeatureCLFLUSHOPT,
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FeatureCMPXCHG16B,
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FeatureF16C,
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FeatureFMA,
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FeatureFSGSBase,
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FeatureFXSR,
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FeatureFastLZCNT,
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FeatureLAHFSAHF,
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FeatureLZCNT,
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FeatureMMX,
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FeatureMOVBE,
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FeatureMWAITX,
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FeaturePCLMUL,
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FeaturePOPCNT,
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FeaturePRFCHW,
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FeatureRDRAND,
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FeatureRDSEED,
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FeatureSHA,
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FeatureSMAP,
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FeatureSSE4A,
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FeatureSlowSHLD,
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FeatureX87,
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FeatureXSAVE,
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FeatureXSAVEC,
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FeatureXSAVEOPT,
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FeatureXSAVES]>;
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def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
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@ -33,3 +33,4 @@
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; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
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; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
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; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
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; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
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@ -3,6 +3,8 @@
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; Eg: zext(or(setcc(cmp), setcc(cmp))) -> shr(or(lzcnt, lzcnt))
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; Test one 32-bit input, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp0(i32 %a) {
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@ -46,6 +46,7 @@
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefix=FAST
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefix=FAST
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefix=FAST
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=FAST
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; Other chips with slow unaligned memory accesses
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@ -17,6 +17,7 @@
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; RUN: llc < %s -march=x86-64 -mcpu=bdver2 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=bdver3 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=bdver4 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=znver1 | FileCheck %s
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; Verify that for the X86_64 processors that are known to have poor latency
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; double precision shift instructions we do not generate 'shld' or 'shrd'
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