[DAGCombiner] fold select-of-constants based on sign-bit test
Examples: i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1 i8 X < 0 ? C1 : 0 --> (X >>s 7) & C1 This is a small generalization of a fold requested in PR43650: https://bugs.llvm.org/show_bug.cgi?id=43650 The sign-bit of the condition operand can be used as a mask for the true operand: https://rise4fun.com/Alive/paT Note that we already handle some of the patterns (isNegative + scalar) because there's an over-specialized, yet over-reaching fold for that in foldSelectCCToShiftAnd(). It doesn't use any TLI hooks, so I can't easily rip out that code even though we're duplicating part of it here. This fold is guarded by TLI.convertSelectOfConstantsToMath(), so it should not cause problems for targets that prefer select over shift. Also worth noting: I thought we could generalize this further to include the case where the true operand of the select is not constant, but Alive says that may allow poison to pass through where it does not in the original select form of the code. Differential Revision: https://reviews.llvm.org/D68949 llvm-svn: 374902
This commit is contained in:
Sanjay Patel
parent
b18170660e
commit
d545c9056e
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@ -8173,6 +8173,43 @@ static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
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}
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}
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/// If a (v)select has a condition value that is a sign-bit test, try to smear
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/// the condition operand sign-bit across the value width and use it as a mask.
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static SDValue foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) {
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SDValue Cond = N->getOperand(0);
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SDValue C1 = N->getOperand(1);
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SDValue C2 = N->getOperand(2);
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assert(isConstantOrConstantVector(C1) && isConstantOrConstantVector(C2) &&
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"Expected select-of-constants");
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EVT VT = N->getValueType(0);
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if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() ||
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VT != Cond.getOperand(0).getValueType())
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return SDValue();
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// The inverted-condition + commuted-select variants of these patterns are
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// canonicalized to these forms in IR.
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SDValue X = Cond.getOperand(0);
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SDValue CondC = Cond.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(CondC) &&
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isAllOnesOrAllOnesSplat(C2)) {
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// i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1
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SDLoc DL(N);
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SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT);
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SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
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return DAG.getNode(ISD::OR, DL, VT, Sra, C1);
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}
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if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) {
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// i8 X < 0 ? C1 : 0 --> (X >>s 7) & C1
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SDLoc DL(N);
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SDValue ShAmtC = DAG.getConstant(X.getScalarValueSizeInBits() - 1, DL, VT);
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SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
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return DAG.getNode(ISD::AND, DL, VT, Sra, C1);
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}
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return SDValue();
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}
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SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
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SDValue Cond = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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@ -8248,6 +8285,9 @@ SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
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SDValue ShAmtC = DAG.getConstant(C1Val.exactLogBase2(), DL, VT);
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return DAG.getNode(ISD::SHL, DL, VT, Cond, ShAmtC);
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}
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if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG))
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return V;
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}
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return SDValue();
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@ -8623,6 +8663,9 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
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return DAG.getNode(ISD::SHL, DL, VT, ZextCond, ShAmtC);
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}
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if (SDValue V = foldSelectOfConstantsUsingSra(N, DAG))
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return V;
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// The general case for select-of-constants:
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// vselect <N x i1> Cond, C1, C2 --> xor (and (sext Cond), (C1^C2)), C2
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// ...but that only makes sense if a vselect is slower than 2 logic ops, so
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@ -4,10 +4,9 @@
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define i8 @isnonneg_i8(i8 %x) {
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; CHECK-LABEL: isnonneg_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb %dil, %dil
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; CHECK-NEXT: movl $42, %ecx
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; CHECK-NEXT: movl $255, %eax
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; CHECK-NEXT: cmovnsl %ecx, %eax
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarb $7, %al
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; CHECK-NEXT: orb $42, %al
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%cond = icmp sgt i8 %x, -1
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@ -18,10 +17,9 @@ define i8 @isnonneg_i8(i8 %x) {
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define i16 @isnonneg_i16(i16 %x) {
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; CHECK-LABEL: isnonneg_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testw %di, %di
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; CHECK-NEXT: movl $542, %ecx # imm = 0x21E
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; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF
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; CHECK-NEXT: cmovnsl %ecx, %eax
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; CHECK-NEXT: movswl %di, %eax
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; CHECK-NEXT: sarl $15, %eax
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; CHECK-NEXT: orl $542, %eax # imm = 0x21E
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%cond = icmp sgt i16 %x, -1
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@ -32,10 +30,9 @@ define i16 @isnonneg_i16(i16 %x) {
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define i32 @isnonneg_i32(i32 %x) {
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; CHECK-LABEL: isnonneg_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: movl $-42, %ecx
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovnsl %ecx, %eax
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: orl $-42, %eax
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; CHECK-NEXT: retq
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%cond = icmp sgt i32 %x, -1
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%r = select i1 %cond, i32 -42, i32 -1
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@ -45,10 +42,9 @@ define i32 @isnonneg_i32(i32 %x) {
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define i64 @isnonneg_i64(i64 %x) {
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; CHECK-LABEL: isnonneg_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: movl $2342342, %ecx # imm = 0x23BDC6
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: cmovnsq %rcx, %rax
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: sarq $63, %rax
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; CHECK-NEXT: orq $2342342, %rax # imm = 0x23BDC6
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; CHECK-NEXT: retq
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%cond = icmp sgt i64 %x, -1
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%r = select i1 %cond, i64 2342342, i64 -1
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@ -58,10 +54,10 @@ define i64 @isnonneg_i64(i64 %x) {
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define <16 x i8> @isnonneg_v16i8(<16 x i8> %x) {
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; CHECK-LABEL: isnonneg_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtb %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: por {{.*}}(%rip), %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtb %xmm0, %xmm1
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; CHECK-NEXT: por {{.*}}(%rip), %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%cond = icmp sgt <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%r = select <16 x i1> %cond, <16 x i8> <i8 12, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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@ -71,9 +67,7 @@ define <16 x i8> @isnonneg_v16i8(<16 x i8> %x) {
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define <8 x i16> @isnonneg_v8i16(<8 x i16> %x) {
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; CHECK-LABEL: isnonneg_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtw %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: psraw $15, %xmm0
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; CHECK-NEXT: por {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp sgt <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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@ -84,9 +78,7 @@ define <8 x i16> @isnonneg_v8i16(<8 x i16> %x) {
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define <4 x i32> @isnonneg_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: isnonneg_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: por {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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@ -97,18 +89,8 @@ define <4 x i32> @isnonneg_v4i32(<4 x i32> %x) {
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define <2 x i64> @isnonneg_v2i64(<2 x i64> %x) {
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; CHECK-LABEL: isnonneg_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [18446744071562067967,18446744071562067967]
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; CHECK-NEXT: pand %xmm3, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
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; CHECK-NEXT: por %xmm0, %xmm1
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: por {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp sgt <2 x i64> %x, <i64 -1, i64 -1>
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@ -182,10 +164,8 @@ define <16 x i8> @isneg_v16i8(<16 x i8> %x) {
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define <8 x i16> @isneg_v8i16(<8 x i16> %x) {
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; CHECK-LABEL: isneg_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtw %xmm0, %xmm1
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: psraw $15, %xmm0
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp slt <8 x i16> %x, zeroinitializer
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%r = select <8 x i1> %cond, <8 x i16> <i16 1, i16 542, i16 542, i16 542, i16 542, i16 542, i16 542, i16 1>, <8 x i16> zeroinitializer
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@ -195,10 +175,8 @@ define <8 x i16> @isneg_v8i16(<8 x i16> %x) {
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define <4 x i32> @isneg_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: isneg_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pcmpgtd %xmm0, %xmm1
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp slt <4 x i32> %x, zeroinitializer
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%r = select <4 x i1> %cond, <4 x i32> <i32 0, i32 42, i32 -42, i32 1>, <4 x i32> zeroinitializer
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@ -208,15 +186,8 @@ define <4 x i32> @isneg_v4i32(<4 x i32> %x) {
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define <2 x i64> @isneg_v2i64(<2 x i64> %x) {
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; CHECK-LABEL: isneg_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
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; CHECK-NEXT: pxor %xmm1, %xmm0
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; CHECK-NEXT: movdqa %xmm1, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
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; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
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; CHECK-NEXT: pand %xmm2, %xmm1
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%cond = icmp slt <2 x i64> %x, zeroinitializer
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