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mark frem as expand for all legal fp types on x86, regardless of whether 

we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
This commit is contained in:
Chris Lattner 2008-03-07 06:36:32 +00:00
parent 92e52c636f
commit d4defb00df
2 changed files with 9 additions and 3 deletions
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5
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -215,7 +215,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::FREM , MVT::f32 , Expand);
setOperationAction(ISD::FREM , MVT::f64 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand);
setOperationAction(ISD::FREM , MVT::f80 , Expand);
setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
setOperationAction(ISD::CTPOP , MVT::i8 , Expand); setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
@ -358,10 +360,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// We don't support sin/cos/fmod // We don't support sin/cos/fmod
setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
// Expand FP immediates into loads from the stack, except for the special // Expand FP immediates into loads from the stack, except for the special
// cases we handle. // cases we handle.
@ -398,7 +398,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// We don't support sin/cos/fmod // We don't support sin/cos/fmod
setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
// Special cases we handle for FP constants. // Special cases we handle for FP constants.
addLegalFPImmediate(APFloat(+0.0f)); // xorps addLegalFPImmediate(APFloat(+0.0f)); // xorps

7
llvm/test/CodeGen/X86/2008-03-06-frem-fpstack.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386
; PR2122
define float @func(float %a, float %b) nounwind {
entry:
%tmp3 = frem float %a, %b ; <float> [#uses=1]
ret float %tmp3
}