[GlobalISel][AArch64] Add isel support for G_INSERT_VECTOR_ELT on v2s32s
This adds support for v2s32 vector inserts, and updates the selection + regbankselect tests for G_INSERT_VECTOR_ELT. Differential Revision: https://reviews.llvm.org/D59910 llvm-svn: 357318
This commit is contained in:
Jessica Paquette
parent
d413f41de6
commit
d3ffd47df9
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@ -2561,11 +2561,7 @@ bool AArch64InstructionSelector::selectInsertElt(
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// Get information on the destination.
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unsigned DstReg = I.getOperand(0).getReg();
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const LLT DstTy = MRI.getType(DstReg);
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if (DstTy.getSizeInBits() < 128) {
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// TODO: Handle unpacked vectors.
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LLVM_DEBUG(dbgs() << "Unpacked vectors not supported yet!");
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return false;
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}
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unsigned VecSize = DstTy.getSizeInBits();
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// Get information on the element we want to insert into the destination.
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unsigned EltReg = I.getOperand(2).getReg();
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@ -2585,7 +2581,50 @@ bool AArch64InstructionSelector::selectInsertElt(
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unsigned SrcReg = I.getOperand(1).getReg();
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const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
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MachineIRBuilder MIRBuilder(I);
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emitLaneInsert(DstReg, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder);
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if (VecSize < 128) {
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// If the vector we're inserting into is smaller than 128 bits, widen it
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// to 128 to do the insert.
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MachineInstr *ScalarToVec = emitScalarToVector(
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VecSize, &AArch64::FPR128RegClass, SrcReg, MIRBuilder);
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if (!ScalarToVec)
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return false;
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SrcReg = ScalarToVec->getOperand(0).getReg();
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}
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// Create an insert into a new FPR128 register.
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// Note that if our vector is already 128 bits, we end up emitting an extra
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// register.
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MachineInstr *InsMI =
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emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder);
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if (VecSize < 128) {
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// If we had to widen to perform the insert, then we have to demote back to
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// the original size to get the result we want.
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unsigned DemoteVec = InsMI->getOperand(0).getReg();
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const TargetRegisterClass *RC =
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getMinClassForRegBank(*RBI.getRegBank(DemoteVec, MRI, TRI), VecSize);
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if (RC != &AArch64::FPR32RegClass && RC != &AArch64::FPR64RegClass) {
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LLVM_DEBUG(dbgs() << "Unsupported register class!\n");
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return false;
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}
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unsigned SubReg = 0;
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if (!getSubRegForClass(RC, TRI, SubReg))
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return false;
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if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) {
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LLVM_DEBUG(dbgs() << "Unsupported destination size! (" << VecSize
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<< "\n");
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return false;
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}
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MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
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.addReg(DemoteVec, 0, SubReg);
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RBI.constrainGenericRegister(DstReg, *RC, MRI);
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} else {
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// No widening needed.
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InsMI->getOperand(0).setReg(DstReg);
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constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
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}
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I.eraseFromParent();
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return true;
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}
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@ -448,9 +448,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &VecTy = Query.Types[0];
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// TODO: Support destination sizes of < 128 bits.
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// TODO: Support s8 and s16
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return VecTy == v4s32 || VecTy == v2s64;
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return VecTy == v2s32 || VecTy == v4s32 || VecTy == v2s64;
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});
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getActionDefinitionsBuilder(G_BUILD_VECTOR)
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@ -111,3 +111,53 @@ body: |
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32_fpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d1, $s0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(s32) = COPY $s0
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%1:_(<2 x s32>) = COPY $d1
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v2s32_gpr
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: v2s32_gpr
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; CHECK: liveins: $d0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
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; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
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; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
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; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK: RET_ReallyLR implicit $d0
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%0:_(s32) = COPY $w0
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%1:_(<2 x s32>) = COPY $d0
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%3:_(s32) = G_CONSTANT i32 1
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%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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@ -104,3 +104,61 @@ body: |
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32_fpr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d1, $s0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
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; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s32) = COPY $s0
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%1:fpr(<2 x s32>) = COPY $d1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v2s32_gpr
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: v2s32_gpr
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; CHECK: liveins: $d0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:gpr(s32) = COPY $w0
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%1:fpr(<2 x s32>) = COPY $d0
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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