diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index b76f2288c646..d9be9b6c39cd 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -768,7 +768,8 @@ private:
     // We allow splitting of non-volatile loads and stores where the type is an
     // integer type. These may be used to implement 'memcpy' or other "transfer
     // of bits" patterns.
-    bool IsSplittable = Ty->isIntegerTy() && !IsVolatile;
+    bool IsSplittable =
+        Ty->isIntegerTy() && !IsVolatile && DL.typeSizeEqualsStoreSize(Ty);
 
     insertUse(I, Offset, Size, IsSplittable);
   }
@@ -3989,6 +3990,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
     SplitLoads.clear();
 
     IntegerType *Ty = cast<IntegerType>(LI->getType());
+    assert(Ty->getBitWidth() % 8 == 0);
     uint64_t LoadSize = Ty->getBitWidth() / 8;
     assert(LoadSize > 0 && "Cannot have a zero-sized integer load!");
 
@@ -4113,6 +4115,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
   for (StoreInst *SI : Stores) {
     auto *LI = cast<LoadInst>(SI->getValueOperand());
     IntegerType *Ty = cast<IntegerType>(LI->getType());
+    assert(Ty->getBitWidth() % 8 == 0);
     uint64_t StoreSize = Ty->getBitWidth() / 8;
     assert(StoreSize > 0 && "Cannot have a zero-sized integer store!");
 
diff --git a/llvm/test/Transforms/SROA/irregular-type.ll b/llvm/test/Transforms/SROA/irregular-type.ll
new file mode 100644
index 000000000000..db1cb9c2a077
--- /dev/null
+++ b/llvm/test/Transforms/SROA/irregular-type.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -sroa -S | FileCheck %s
+
+%S = type { [4 x i8] }
+
+; Ensure the load/store of integer types whose size is not equal to the store
+; size are not split.
+
+define i8 @foo(i23 %0) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    [[DOTSROA_0:%.*]] = alloca [3 x i8], align 8
+; CHECK-NEXT:    [[DOTSROA_0_0__SROA_CAST1:%.*]] = bitcast [3 x i8]* [[DOTSROA_0]] to i23*
+; CHECK-NEXT:    store i23 [[TMP0:%.*]], i23* [[DOTSROA_0_0__SROA_CAST1]], align 8
+; CHECK-NEXT:    [[DOTSROA_0_1__SROA_IDX2:%.*]] = getelementptr inbounds [3 x i8], [3 x i8]* [[DOTSROA_0]], i64 0, i64 1
+; CHECK-NEXT:    [[DOTSROA_0_1__SROA_0_1_:%.*]] = load i8, i8* [[DOTSROA_0_1__SROA_IDX2]], align 1
+; CHECK-NEXT:    ret i8 [[DOTSROA_0_1__SROA_0_1_]]
+;
+Entry:
+  %1 = alloca %S
+  %2 = bitcast %S* %1 to i23*
+  store i23 %0, i23* %2
+  %3 = getelementptr inbounds %S, %S* %1, i64 0, i32 0, i32 1
+  %4 = load i8, i8* %3
+  ret i8 %4
+}
+
+define i32 @bar(i16 %0) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:  Entry:
+; CHECK-NEXT:    [[DOTSROA_0:%.*]] = alloca [3 x i8], align 8
+; CHECK-NEXT:    [[DOTSROA_0_0__SROA_CAST2:%.*]] = bitcast [3 x i8]* [[DOTSROA_0]] to i16*
+; CHECK-NEXT:    store i16 [[TMP0:%.*]], i16* [[DOTSROA_0_0__SROA_CAST2]], align 8
+; CHECK-NEXT:    [[DOTSROA_0_0_Q_SROA_CAST1:%.*]] = bitcast [3 x i8]* [[DOTSROA_0]] to i17*
+; CHECK-NEXT:    [[DOTSROA_0_0__SROA_0_0_:%.*]] = load i17, i17* [[DOTSROA_0_0_Q_SROA_CAST1]], align 8
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i17 [[DOTSROA_0_0__SROA_0_0_]] to i32
+; CHECK-NEXT:    ret i32 [[TMP1]]
+;
+Entry:
+  %1 = alloca %S
+  %2 = bitcast %S* %1 to i16*
+  store i16 %0, i16* %2
+  %3 = getelementptr inbounds %S, %S* %1, i64 0, i32 0
+  %q = bitcast [4 x i8]* %3 to i17*
+  %4 = load i17, i17* %q
+  %5 = zext i17 %4 to i32
+  ret i32 %5
+}
diff --git a/llvm/test/Transforms/SROA/slice-width.ll b/llvm/test/Transforms/SROA/slice-width.ll
index 5f4af9cc45e5..2deef736de25 100644
--- a/llvm/test/Transforms/SROA/slice-width.ll
+++ b/llvm/test/Transforms/SROA/slice-width.ll
@@ -15,18 +15,11 @@ define void @no_split_on_non_byte_width(i32) {
 ; CHECK-NEXT:    [[ARG_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[ARG_SROA_3_0_EXTRACT_SHIFT]] to i24
 ; CHECK-NEXT:    br label [[LOAD_I32:%.*]]
 ; CHECK:       load_i32:
-; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_R0:%.*]] = load i8, i8* [[ARG_SROA_0]], align 8
-; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_EXT:%.*]] = zext i24 [[ARG_SROA_3_0_EXTRACT_TRUNC]] to i32
-; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_SHIFT:%.*]] = shl i32 [[ARG_SROA_3_0_INSERT_EXT]], 8
-; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_MASK:%.*]] = and i32 undef, 255
-; CHECK-NEXT:    [[ARG_SROA_3_0_INSERT_INSERT:%.*]] = or i32 [[ARG_SROA_3_0_INSERT_MASK]], [[ARG_SROA_3_0_INSERT_SHIFT]]
-; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_EXT:%.*]] = zext i8 [[ARG_SROA_0_0_ARG_SROA_0_0_R0]] to i32
-; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_MASK:%.*]] = and i32 [[ARG_SROA_3_0_INSERT_INSERT]], -256
-; CHECK-NEXT:    [[ARG_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[ARG_SROA_0_0_INSERT_MASK]], [[ARG_SROA_0_0_INSERT_EXT]]
+; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_R01:%.*]] = load i8, i8* [[ARG_SROA_0]], align 8
 ; CHECK-NEXT:    br label [[LOAD_I1:%.*]]
 ; CHECK:       load_i1:
-; CHECK-NEXT:    [[ARG_SROA_0_0_P1_SROA_CAST2:%.*]] = bitcast i8* [[ARG_SROA_0]] to i1*
-; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_T1:%.*]] = load i1, i1* [[ARG_SROA_0_0_P1_SROA_CAST2]], align 8
+; CHECK-NEXT:    [[ARG_SROA_0_0_P1_SROA_CAST4:%.*]] = bitcast i8* [[ARG_SROA_0]] to i1*
+; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_T1:%.*]] = load i1, i1* [[ARG_SROA_0_0_P1_SROA_CAST4]], align 8
 ; CHECK-NEXT:    ret void
 ;
   %arg = alloca i32 , align 8
@@ -116,6 +109,7 @@ define i32 @memcpy_vec3float_widening(%S.vec3float* %x) {
 ; CHECK-NEXT:    store <3 x float> [[TMP1_SROA_0_0_VEC_EXTRACT]], <3 x float>* [[TMP1_SROA_0_0_TMP1_SROA_0_0__SROA_CAST2_SROA_CAST]], align 4
 ; CHECK-NEXT:    [[RESULT:%.*]] = call i32 @memcpy_vec3float_helper(%S.vec3float* [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[RESULT]]
+;
 entry:
   ; Create a temporary variable %tmp1 and copy %x[0] into it
   %tmp1 = alloca %S.vec3float, align 4