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Codegen x < 0 | y < 0 as (x|y) < 0. This allows us to compile this to: 

_foo:
        or r2, r4, r3
        srwi r3, r2, 31
        blr

instead of:

_foo:
        srwi r2, r4, 31
        srwi r3, r3, 31
        or r3, r2, r3
        blr

llvm-svn: 21544
This commit is contained in:
Chris Lattner 2005-04-25 21:03:25 +00:00
parent e093c6f565
commit d373ff64aa
1 changed files with 4 additions and 1 deletions
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5
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -809,6 +809,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
}
return false;
// TODO we could handle some SRA cases here.
default: break;
}
@ -1061,11 +1062,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// (X != 0) | (Y != 0) -> (X|Y != 0)
// (X == 0) & (Y == 0) -> (X|Y == 0)
// (X < 0) | (Y < 0) -> (X|Y < 0)
if (LR == RR && isa<ConstantSDNode>(LR) &&
cast<ConstantSDNode>(LR)->getValue() == 0 &&
Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
(Op2 == ISD::SETNE && Opcode == ISD::OR))
(Op2 == ISD::SETNE && Opcode == ISD::OR) ||
(Op2 == ISD::SETLT && Opcode == ISD::OR))
return getSetCC(Op2, VT,
getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
}