[ARM] Tidy up and organise better ARM.td. NFC.
This patch tidies up and organises ARM.td so that it is easier to understandand and extend in the future. Reviewed by: @hahn, @rovka Differential Revision: https://reviews.llvm.org/D35248 llvm-svn: 307897
This commit is contained in:
Javed Absar
parent
f69d7b0495
commit
d32f9c8190
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@ -16,145 +16,173 @@
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Helper classes.
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//
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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class Architecture<string fname, string aname, list<SubtargetFeature> features >
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: SubtargetFeature<fname, "ARMArch", aname,
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!strconcat(aname, " architecture"), features>;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
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"Thumb mode">;
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def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode",
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"true", "Thumb mode">;
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def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat",
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"true", "Use software floating "
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"point features.">;
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def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software floating point features.">;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
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"Enable VFP3 instructions",
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[FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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"Does not support ARM mode execution",
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[ModeThumb]>;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision floating point">;
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def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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"Enable VFP4 instructions",
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[FeatureVFP3, FeatureFP16]>;
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
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"true", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Enable full half-precision floating point",
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[FeatureFPARMv8]>;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict FP to 16 double registers">;
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def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
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"true",
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"Enable divide instructions in Thumb">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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"HasHardwareDivideInARM", "true",
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"Enable divide instructions in ARM mode">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
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"Has v7 clrex instruction">;
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// Floating Point, HW Division and Neon Support
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
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"Enable VFP3 instructions",
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[FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision "
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"floating point">;
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def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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"Enable VFP4 instructions",
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[FeatureVFP3, FeatureFP16]>;
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
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"true", "Enable ARMv8 FP",
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[FeatureVFP4]>;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Enable full half-precision "
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"floating point",
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[FeatureFPARMv8]>;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports "
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"single precision only">;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict FP to 16 double registers">;
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def FeatureHWDivThumb : SubtargetFeature<"hwdiv",
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"HasHardwareDivideInThumb", "true",
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"Enable divide instructions in Thumb">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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"HasHardwareDivideInARM", "true",
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"Enable divide instructions in ARM mode">;
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// Atomic Support
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb/dsb) instructions">;
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def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
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"Has v7 clrex instruction">;
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def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
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"HasAcquireRelease", "true",
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"Has v8 acquire/release (lda/ldaex etc) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports single precision only">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable support for Performance Monitor extensions">;
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def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
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"Enable support for TrustZone security extensions">;
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def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
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"Enable support for ARMv8-M Security Extensions">;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable support for Cryptography extensions",
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[FeatureNEON]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable support for CRC instructions">;
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"Has v8 acquire/release (lda/ldaex "
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" etc) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable support for Performance "
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"Monitor extensions">;
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// TrustZone Security Extensions
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def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
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"Enable support for TrustZone "
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"security extensions">;
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def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
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"Enable support for ARMv8-M "
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"Security Extensions">;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable support for "
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"Cryptography extensions",
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[FeatureNEON]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable support for CRC instructions">;
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// Not to be confused with FeatureHasRetAddrStack (return address stack)
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable Reliability, Availability and Serviceability extensions">;
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def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
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"Enable fast computation of positive address offsets">;
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def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable Reliability, Availability "
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"and Serviceability extensions">;
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// Cyclone has preferred instructions for zeroing VFP registers, which can
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// execute in 0 cycles.
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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// Fast computation of non-negative address offsets
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def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
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"Enable fast computation of "
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"positive address offsets">;
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// Whether or not it may be profitable to unpredicate certain instructions
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// during if conversion.
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// Fast execution of AES crypto operations
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def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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// Cyclone can zero VFP registers in 0 cycles.
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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// Whether it is profitable to unpredicate certain instructions during if-conversion
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def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
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"IsProfitableToUnpredicate",
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"true",
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"IsProfitableToUnpredicate", "true",
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"Is profitable to unpredicate">;
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// Some targets (e.g. Swift) have microcoded VGETLNi32.
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def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
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"HasSlowVGETLNi32", "true",
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"Has slow VGETLNi32 - prefer VMOV">;
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def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
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"HasSlowVGETLNi32", "true",
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"Has slow VGETLNi32 - prefer VMOV">;
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// Some targets (e.g. Swift) have microcoded VDUP32.
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def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
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"Has slow VDUP32 - prefer VMOV">;
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def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
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"true",
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"Has slow VDUP32 - prefer VMOV">;
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// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
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// for scalar FP, as this allows more effective execution domain optimization.
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def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
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"true", "Prefer VMOVSR">;
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def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
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"true", "Prefer VMOVSR">;
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// Swift has ISHST barriers compatible with Atomic Release semantics but weaker
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// than ISH
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def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
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"true", "Prefer ISHST barriers">;
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"true", "Prefer ISHST barriers">;
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// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
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def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
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"Has muxed AGU and NEON/FPU">;
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def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits",
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"true",
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"Has muxed AGU and NEON/FPU">;
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// On some targets, a VLDM/VSTM starting with an odd register number needs more
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// microops than single VLDRS.
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// Whether VLDM/VSTM starting with odd register number need more microops
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// than single VLDRS
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def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
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"true", "VLDM/VSTM starting with an odd register is slow">;
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"true", "VLDM/VSTM starting "
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"with an odd register is slow">;
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// Some targets have a renaming dependency when loading into D subregisters.
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def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
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"SlowLoadDSubregister", "true",
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"Loading into D subregs is slow">;
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// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
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def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
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"DontWidenVMOVS", "true",
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"Don't widen VMOVS to VMOVD">;
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// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
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def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
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"Expand VFP/NEON MLA/MLS instructions">;
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def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx",
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"ExpandMLx", "true",
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"Expand VFP/NEON MLA/MLS instructions">;
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// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
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def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
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@ -162,15 +190,18 @@ def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
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// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
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// VFP to NEON, as an execution domain optimization.
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def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
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"true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
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def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs",
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"UseNEONForFPMovs", "true",
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"Convert VMOVSR, VMOVRS, "
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"VMOVS to NEON">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations. This affects instruction selection and should
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// only be enabled if the handling of denormals is not important.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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def FeatureNEONForFP : SubtargetFeature<"neonfp",
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"UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// On some processors, VLDn instructions that access unaligned data take one
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// extra cycle. Take that into account when computing operand latencies.
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@ -181,18 +212,18 @@ def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
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// Some processors have a nonpipelined VFP coprocessor.
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def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
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"NonpipelinedVFP", "true",
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"VFP instructions are not pipelined">;
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"VFP instructions are not pipelined">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
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def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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@ -213,14 +244,16 @@ def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
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"true",
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"Disable +1 predication cost for instructions updating CPSR">;
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def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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"AvoidMOVsShifterOperand", "true",
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"Avoid movs instructions with shifter operand">;
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def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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"AvoidMOVsShifterOperand", "true",
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"Avoid movs instructions with "
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"shifter operand">;
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// Some processors perform return stack prediction. CodeGen should avoid issue
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// "normal" call instructions to callees which do not return.
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def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
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"Has return address stack">;
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def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
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"HasRetAddrStack", "true",
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"Has return address stack">;
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// Some processors have no branch predictor, which changes the expected cost of
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// taking a branch which affects the choice of whether to use predicated
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@ -230,63 +263,80 @@ def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
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"Has no branch predictor">;
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/// DSP extension.
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
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"Supports DSP instructions in ARM and/or Thumb2">;
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def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
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"Supports DSP instructions in "
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"ARM and/or Thumb2">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
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def FeatureVirtualization : SubtargetFeature<"virtualization",
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"HasVirtualization", "true",
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"Supports Virtualization extension",
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[FeatureHWDivThumb, FeatureHWDivARM]>;
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"HasVirtualization", "true",
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"Supports Virtualization extension",
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[FeatureHWDivThumb, FeatureHWDivARM]>;
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// M-series ISA
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def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
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"Is microcontroller profile ('M' series)">;
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// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
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// See ARMInstrInfo.td for details.
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def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
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"NaCl trap">;
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// R-series ISA
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def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
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"Is realtime profile ('R' series)">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
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"Generate calls via indirect call "
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"instructions">;
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def FeatureExecuteOnly : SubtargetFeature<"execute-only",
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"GenExecuteOnly", "true",
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"Enable the generation of "
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"execute only code.">;
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def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
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"Reserve R9, making it unavailable"
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||||
" as GPR">;
|
||||
|
||||
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
|
||||
"Don't use movt/movw pairs for "
|
||||
"32-bit imms">;
|
||||
|
||||
def FeatureNoNegativeImmediates
|
||||
: SubtargetFeature<"no-neg-immediates",
|
||||
"NegativeImmediates", "false",
|
||||
"Convert immediates and instructions "
|
||||
"to their negated or complemented "
|
||||
"equivalent when the immediate does "
|
||||
"not fit in the encoding.">;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM architecture class
|
||||
//
|
||||
|
||||
// A-series ISA
|
||||
def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
|
||||
"Is application profile ('A' series)">;
|
||||
|
||||
// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
|
||||
// See ARMInstrInfo.td for details.
|
||||
def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
|
||||
"NaCl trap">;
|
||||
// R-series ISA
|
||||
def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
|
||||
"Is realtime profile ('R' series)">;
|
||||
|
||||
def FeatureStrictAlign : SubtargetFeature<"strict-align",
|
||||
"StrictAlign", "true",
|
||||
"Disallow all unaligned memory "
|
||||
"access">;
|
||||
// M-series ISA
|
||||
def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
|
||||
"Is microcontroller profile ('M' series)">;
|
||||
|
||||
def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
|
||||
"Generate calls via indirect call "
|
||||
"instructions">;
|
||||
|
||||
def FeatureExecuteOnly
|
||||
: SubtargetFeature<"execute-only", "GenExecuteOnly", "true",
|
||||
"Enable the generation of execute only code.">;
|
||||
def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
|
||||
"Enable Thumb2 instructions">;
|
||||
|
||||
def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
|
||||
"Reserve R9, making it unavailable as "
|
||||
"GPR">;
|
||||
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
|
||||
"Does not support ARM mode execution",
|
||||
[ModeThumb]>;
|
||||
|
||||
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
|
||||
"Don't use movt/movw pairs for 32-bit "
|
||||
"imms">;
|
||||
|
||||
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
|
||||
"NegativeImmediates", "false",
|
||||
"Convert immediates and instructions "
|
||||
"to their negated or complemented "
|
||||
"equivalent when the immediate does "
|
||||
"not fit in the encoding.">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM ISAa.
|
||||
|
|
@ -294,43 +344,57 @@ def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
|
|||
|
||||
def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
|
||||
"Support ARM v4T instructions">;
|
||||
|
||||
def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
|
||||
"Support ARM v5T instructions",
|
||||
[HasV4TOps]>;
|
||||
|
||||
def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
|
||||
"Support ARM v5TE, v5TEj, and v5TExp instructions",
|
||||
"Support ARM v5TE, v5TEj, and "
|
||||
"v5TExp instructions",
|
||||
[HasV5TOps]>;
|
||||
|
||||
def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
|
||||
"Support ARM v6 instructions",
|
||||
[HasV5TEOps]>;
|
||||
|
||||
def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
|
||||
"Support ARM v6M instructions",
|
||||
[HasV6Ops]>;
|
||||
|
||||
def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
|
||||
"Support ARM v8M Baseline instructions",
|
||||
[HasV6MOps]>;
|
||||
|
||||
def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
|
||||
"Support ARM v6k instructions",
|
||||
[HasV6Ops]>;
|
||||
|
||||
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
|
||||
"Support ARM v6t2 instructions",
|
||||
[HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
|
||||
|
||||
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
|
||||
"Support ARM v7 instructions",
|
||||
[HasV6T2Ops, FeaturePerfMon,
|
||||
FeatureV7Clrex]>;
|
||||
|
||||
def HasV8MMainlineOps :
|
||||
SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
|
||||
"Support ARM v8M Mainline instructions",
|
||||
[HasV7Ops]>;
|
||||
|
||||
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
|
||||
"Support ARM v8 instructions",
|
||||
[HasV7Ops, FeatureAcquireRelease]>;
|
||||
|
||||
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
|
||||
"Support ARM v8.1a instructions",
|
||||
[HasV8Ops]>;
|
||||
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
|
||||
|
||||
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
|
||||
"Support ARM v8.2a instructions",
|
||||
[HasV8_1aOps]>;
|
||||
def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
|
||||
"Support ARM v8M Mainline instructions",
|
||||
[HasV7Ops]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -386,11 +450,17 @@ def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
|
|||
def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
|
||||
"Cortex-M3 ARM processors", []>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM schedules.
|
||||
// ARM Helper classes.
|
||||
//
|
||||
|
||||
include "ARMSchedule.td"
|
||||
class Architecture<string fname, string aname, list<SubtargetFeature> features>
|
||||
: SubtargetFeature<fname, "ARMArch", aname,
|
||||
!strconcat(aname, " architecture"), features>;
|
||||
|
||||
class ProcNoItin<string Name, list<SubtargetFeature> Features>
|
||||
: Processor<Name, NoItineraries, Features>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -546,6 +616,12 @@ def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
|
|||
def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM schedules.
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
include "ARMSchedule.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ARM processors
|
||||
//
|
||||
|
|
@ -553,6 +629,9 @@ def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
|
|||
// Dummy CPU, used to target architectures
|
||||
def : ProcessorModel<"generic", CortexA8Model, []>;
|
||||
|
||||
// FIXME: Several processors below are not using their own scheduler
|
||||
// model, but one of similar/previous processor. These should be fixed.
|
||||
|
||||
def : ProcNoItin<"arm8", [ARMv4]>;
|
||||
def : ProcNoItin<"arm810", [ARMv4]>;
|
||||
def : ProcNoItin<"strongarm", [ARMv4]>;
|
||||
|
|
@ -612,7 +691,6 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
|
|||
FeatureVFP2,
|
||||
FeatureHasSlowFPVMLx]>;
|
||||
|
||||
// FIXME: A5 has currently the same Schedule model as A8
|
||||
def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureTrustZone,
|
||||
|
|
@ -656,7 +734,6 @@ def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
|
|||
FeatureCheckVLDnAlign,
|
||||
FeatureMP]>;
|
||||
|
||||
// FIXME: A12 has currently the same Schedule model as A9
|
||||
def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureTrustZone,
|
||||
|
|
@ -666,7 +743,6 @@ def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
|
|||
FeatureVirtualization,
|
||||
FeatureMP]>;
|
||||
|
||||
// FIXME: A15 has currently the same Schedule model as A9.
|
||||
def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
|
||||
FeatureDontWidenVMOVS,
|
||||
FeatureHasRetAddrStack,
|
||||
|
|
@ -678,7 +754,6 @@ def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
|
|||
FeatureAvoidPartialCPSR,
|
||||
FeatureVirtualization]>;
|
||||
|
||||
// FIXME: A17 has currently the same Schedule model as A9
|
||||
def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureTrustZone,
|
||||
|
|
@ -688,9 +763,7 @@ def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
|
|||
FeatureAvoidPartialCPSR,
|
||||
FeatureVirtualization]>;
|
||||
|
||||
// FIXME: krait has currently the same Schedule model as A9
|
||||
// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
|
||||
// division features.
|
||||
// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv
|
||||
def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureMuxedUnits,
|
||||
|
|
@ -720,12 +793,10 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
|
|||
FeatureSlowVGETLNi32,
|
||||
FeatureSlowVDUP32]>;
|
||||
|
||||
// FIXME: R4 has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureAvoidPartialCPSR]>;
|
||||
|
||||
// FIXME: R4F has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureSlowFPBrcc,
|
||||
|
|
@ -734,7 +805,6 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
|
|||
FeatureD16,
|
||||
FeatureAvoidPartialCPSR]>;
|
||||
|
||||
// FIXME: R5 has currently the same ProcessorModel as A8.
|
||||
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureVFP3,
|
||||
|
|
@ -744,7 +814,6 @@ def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
|
|||
FeatureHasSlowFPVMLx,
|
||||
FeatureAvoidPartialCPSR]>;
|
||||
|
||||
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
|
||||
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureVFP3,
|
||||
|
|
@ -814,14 +883,14 @@ def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
|
|||
FeatureCRC,
|
||||
FeatureFPAO]>;
|
||||
|
||||
def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
|
||||
FeatureHWDivThumb,
|
||||
FeatureHWDivARM,
|
||||
FeatureCrypto,
|
||||
FeatureCRC,
|
||||
FeatureFPAO,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureCheapPredicableCPSR]>;
|
||||
def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
|
||||
FeatureHWDivThumb,
|
||||
FeatureHWDivARM,
|
||||
FeatureCrypto,
|
||||
FeatureCRC,
|
||||
FeatureFPAO,
|
||||
FeatureAvoidPartialCPSR,
|
||||
FeatureCheapPredicableCPSR]>;
|
||||
|
||||
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
|
||||
FeatureHWDivThumb,
|
||||
|
|
@ -835,7 +904,6 @@ def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
|
|||
FeatureCrypto,
|
||||
FeatureCRC]>;
|
||||
|
||||
// Cyclone is very similar to swift
|
||||
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
|
||||
FeatureHasRetAddrStack,
|
||||
FeatureNEONForFP,
|
||||
|
|
@ -881,9 +949,7 @@ def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "ARMRegisterInfo.td"
|
||||
|
||||
include "ARMRegisterBanks.td"
|
||||
|
||||
include "ARMCallingConv.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -891,7 +957,6 @@ include "ARMCallingConv.td"
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "ARMInstrInfo.td"
|
||||
|
||||
def ARMInstrInfo : InstrInfo;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -912,7 +977,7 @@ def ARMAsmParserVariant : AsmParserVariant {
|
|||
}
|
||||
|
||||
def ARM : Target {
|
||||
// Pull in Instruction Info:
|
||||
// Pull in Instruction Info.
|
||||
let InstructionSet = ARMInstrInfo;
|
||||
let AssemblyWriters = [ARMAsmWriter];
|
||||
let AssemblyParserVariants = [ARMAsmParserVariant];
|
||||
|
|
|
|||
Loading…
Reference in New Issue