[PowerPC] Implementation of 128-bit Binary Vector Rotate builtins
This patch implements 128-bit Binary Vector Rotate builtins for PowerPC10. Differential Revision: https://reviews.llvm.org/D86819
This commit is contained in:
Albion Fung
parent
c096377905
commit
d30155feaa
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@ -422,6 +422,10 @@ BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "")
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BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "")
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BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "")
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// P10 Vector rotate built-ins.
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BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "")
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BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "")
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// VSX built-ins.
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BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
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@ -7927,6 +7927,18 @@ vec_rl(vector unsigned long long __a, vector unsigned long long __b) {
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}
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#endif
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#ifdef __POWER10_VECTOR__
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_rl(vector signed __int128 __a, vector unsigned __int128 __b) {
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return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector signed __int128)) - __a));
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}
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_rl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
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return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector unsigned __int128)) - __a));
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}
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#endif
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/* vec_rlmi */
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#ifdef __POWER9_VECTOR__
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static __inline__ vector unsigned int __ATTRS_o_ai
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@ -7940,8 +7952,24 @@ vec_rlmi(vector unsigned long long __a, vector unsigned long long __b,
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vector unsigned long long __c) {
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return __builtin_altivec_vrldmi(__a, __c, __b);
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}
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#endif
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#ifdef __POWER10_VECTOR__
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_rlmi(vector unsigned __int128 __a, vector unsigned __int128 __b,
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vector unsigned __int128 __c) {
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return __builtin_altivec_vrlqmi(__a, __c, __b);
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}
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_rlmi(vector signed __int128 __a, vector signed __int128 __b,
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vector signed __int128 __c) {
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return __builtin_altivec_vrlqmi(__a, __c, __b);
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}
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#endif
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/* vec_rlnm */
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#ifdef __POWER9_VECTOR__
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_rlnm(vector unsigned int __a, vector unsigned int __b,
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vector unsigned int __c) {
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@ -7957,6 +7985,42 @@ vec_rlnm(vector unsigned long long __a, vector unsigned long long __b,
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}
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#endif
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#ifdef __POWER10_VECTOR__
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_rlnm(vector unsigned __int128 __a, vector unsigned __int128 __b,
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vector unsigned __int128 __c) {
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// Merge __b and __c using an appropriate shuffle.
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vector unsigned char TmpB = (vector unsigned char)__b;
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vector unsigned char TmpC = (vector unsigned char)__c;
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vector unsigned char MaskAndShift =
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#ifdef __LITTLE_ENDIAN__
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__builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, -1, -1, -1, 16, 0,
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1, -1, -1, -1, -1, -1);
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#else
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__builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1,
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-1, -1, -1, -1, -1, -1, -1);
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#endif
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return __builtin_altivec_vrlqnm(__a, (vector unsigned __int128) MaskAndShift);
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}
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_rlnm(vector signed __int128 __a, vector signed __int128 __b,
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vector signed __int128 __c) {
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// Merge __b and __c using an appropriate shuffle.
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vector unsigned char TmpB = (vector unsigned char)__b;
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vector unsigned char TmpC = (vector unsigned char)__c;
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vector unsigned char MaskAndShift =
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#ifdef __LITTLE_ENDIAN__
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__builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, -1, -1, -1, 16, 0,
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1, -1, -1, -1, -1, -1);
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#else
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__builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1,
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-1, -1, -1, -1, -1, -1, -1);
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#endif
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return __builtin_altivec_vrlqnm(__a, (vector unsigned __int128) MaskAndShift);
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}
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#endif
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/* vec_vrlb */
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static __inline__ vector signed char __ATTRS_o_ai
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@ -17,7 +17,7 @@ vector signed int vsia, vsib;
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vector unsigned int vuia, vuib, vuic;
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vector signed long long vslla, vsllb;
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vector unsigned long long vulla, vullb, vullc;
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vector signed __int128 vsi128a, vsi128b;
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vector signed __int128 vsi128a, vsi128b, vsi128c;
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vector unsigned __int128 vui128a, vui128b, vui128c;
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vector float vfa, vfb;
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vector double vda, vdb;
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@ -1880,3 +1880,53 @@ int test_vec_all_ge_u128(void) {
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// CHECK-NEXT: ret i32
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return vec_all_ge(vui128a, vui128b);
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}
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vector signed __int128 test_vec_rl_s128(void) {
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// CHECK-LABEL: @test_vec_rl_s128(
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// CHECK: sub <1 x i128>
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// CHECK-NEXT: lshr <1 x i128>
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// CHECK-NEXT: or <1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rl(vsi128a, vsi128b);
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}
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vector unsigned __int128 test_vec_rl_u128(void) {
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// CHECK-LABEL: @test_vec_rl_u128(
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// CHECK: sub <1 x i128>
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// CHECK: lshr <1 x i128>
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// CHECK: or <1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rl(vui128a, vui128b);
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}
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vector signed __int128 test_vec_rlnm_s128(void) {
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// CHECK-LABEL: @test_vec_rlnm_s128(
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// CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rlnm(vsi128a, vsi128b, vsi128c);
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}
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vector unsigned __int128 test_vec_rlnm_u128(void) {
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// CHECK-LABEL: @test_vec_rlnm_u128(
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// CHECK-LE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// CHECK-BE: %shuffle.i = shufflevector <16 x i8> %7, <16 x i8> %8, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rlnm(vui128a, vui128b, vui128c);
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}
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vector signed __int128 test_vec_rlmi_s128(void) {
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// CHECK-LABEL: @test_vec_rlmi_s128(
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// CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rlmi(vsi128a, vsi128b, vsi128c);
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}
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vector unsigned __int128 test_vec_rlmi_u128(void) {
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// CHECK-LABEL: @test_vec_rlmi_u128(
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// CHECK: call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>
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// CHECK-NEXT: ret <1 x i128>
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return vec_rlmi(vui128a, vui128b, vui128c);
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}
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@ -1057,6 +1057,15 @@ def int_ppc_altivec_vrldmi :
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[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vrlqnm :
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PowerPC_Vec_Intrinsic<"vrlqnm", [llvm_v1i128_ty],
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[llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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def int_ppc_altivec_vrlqmi :
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PowerPC_Vec_Intrinsic<"vrlqmi", [llvm_v1i128_ty],
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[llvm_v1i128_ty, llvm_v1i128_ty, llvm_v1i128_ty],
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[IntrNoMem]>;
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// Vector Divide Extended Intrinsics.
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def int_ppc_altivec_vdivesw : PowerPC_Vec_WWW_Intrinsic<"vdivesw">;
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def int_ppc_altivec_vdiveuw : PowerPC_Vec_WWW_Intrinsic<"vdiveuw">;
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@ -892,6 +892,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SREM, MVT::v1i128, Legal);
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setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
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setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
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setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
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}
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setOperationAction(ISD::MUL, MVT::v8i16, Legal);
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@ -2111,10 +2111,16 @@ let Predicates = [IsISA3_1] in {
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"vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
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def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
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"vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
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def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", []>;
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def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
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[(set v1i128:$vD,
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(int_ppc_altivec_vrlqnm v1i128:$vA,
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v1i128:$vB))]>;
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def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
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(ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
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"vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,
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"vrlqmi $vD, $vA, $vB", IIC_VecFP,
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[(set v1i128:$vD,
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(int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB,
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v1i128:$vDi))]>,
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RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
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def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
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def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
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@ -2175,6 +2181,9 @@ let Predicates = [IsISA3_1] in {
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(v1i128 (COPY_TO_REGCLASS (LXVRWX xoaddr:$src), VRRC))>;
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def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 64)),
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(v1i128 (COPY_TO_REGCLASS (LXVRDX xoaddr:$src), VRRC))>;
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def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
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(v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
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}
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let Predicates = [IsISA3_1, HasVSX] in {
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@ -0,0 +1,85 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s -check-prefixes=CHECK-LE,CHECK
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s -check-prefixes=CHECK-BE,CHECK
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; This test case aims to test the builtins for vector rotate instructions
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; on Power10.
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define <1 x i128> @test_vrlq(<1 x i128> %x, <1 x i128> %y) {
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; CHECK-LABEL: test_vrlq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vrlq v2, v3, v2
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; CHECK-NEXT: blr
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%shl.i = shl <1 x i128> %y, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> %y, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vrlq_cost_mult8(<1 x i128> %x) {
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; CHECK-LABEL: test_vrlq_cost_mult8:
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; CHECK: # %bb.0:
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; CHECK: vrlq v2, v3, v2
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; CHECK-NEXT: blr
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%shl.i = shl <1 x i128> <i128 16>, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> <i128 16>, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) {
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; CHECK-LABEL: test_vrlq_cost_non_mult8:
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; CHECK: # %bb.0:
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; CHECK: vrlq v2, v3, v2
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; CHECK-NEXT: blr
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%shl.i = shl <1 x i128> <i128 4>, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> <i128 4>, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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define <1 x i128> @test_vrlqmi(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
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; CHECK-LABEL: test_vrlqmi:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vrlqmi v3, v2, v4
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; CHECK-NEXT: vmr v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b)
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
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; CHECK-LABEL: test_vrlqnm:
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; CHECK: # %bb.0: # %entry
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; CHECK-BE: lxvx v5
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; CHECK-BE-NEXT: vperm v3, v3, v4, v5
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; CHECK-LE-NEXT: plxv v5
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; CHECK-LE-NEXT: vperm v3, v4, v3, v5
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; CHECK-NEXT: vrlqnm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%0 = bitcast <1 x i128> %b to <16 x i8>
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%1 = bitcast <1 x i128> %c to <16 x i8>
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%shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%d = bitcast <16 x i8> %shuffle.i to <1 x i128>
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d)
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>)
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>)
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