[globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson Reviewed By: aemerson Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45543 llvm-svn: 331816
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@ -35,6 +35,10 @@ public:
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/// Returns true if MI changed.
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bool tryCombineCopy(MachineInstr &MI);
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/// If \p MI is extend that consumes the result of a load, try to combine it.
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/// Returns true if MI changed.
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bool tryCombineExtendingLoads(MachineInstr &MI);
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/// Try to transform \p MI by using all of the above
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/// combine functions. Returns true if changed.
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bool tryCombine(MachineInstr &MI);
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@ -36,6 +36,38 @@ bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
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return false;
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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return tryCombineCopy(MI);
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bool CombinerHelper::tryCombineExtendingLoads(MachineInstr &MI) {
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(1).getReg();
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if (MI.getOpcode() != TargetOpcode::G_ANYEXT &&
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MI.getOpcode() != TargetOpcode::G_SEXT &&
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MI.getOpcode() != TargetOpcode::G_ZEXT)
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return false;
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LLT DstTy = MRI.getType(DstReg);
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if (!DstTy.isScalar())
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return false;
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if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI)) {
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unsigned PtrReg = DefMI->getOperand(1).getReg();
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MachineMemOperand &MMO = **DefMI->memoperands_begin();
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DEBUG(dbgs() << ".. Combine MI: " << MI;);
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Builder.setInstr(MI);
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Builder.buildLoadInstr(MI.getOpcode() == TargetOpcode::G_SEXT
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? TargetOpcode::G_SEXTLOAD
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: MI.getOpcode() == TargetOpcode::G_ZEXT
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? TargetOpcode::G_ZEXTLOAD
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: TargetOpcode::G_LOAD,
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DstReg, PtrReg, MMO);
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MI.eraseFromParent();
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return true;
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}
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return false;
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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if (tryCombineCopy(MI))
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return true;
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return tryCombineExtendingLoads(MI);;
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}
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@ -53,6 +53,7 @@ FunctionPass *createAArch64CollectLOHPass();
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InstructionSelector *
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createAArch64InstructionSelector(const AArch64TargetMachine &,
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AArch64Subtarget &, AArch64RegisterBankInfo &);
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FunctionPass *createAArch64PreLegalizeCombiner();
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void initializeAArch64A53Fix835769Pass(PassRegistry&);
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void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
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@ -65,6 +66,7 @@ void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
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void initializeAArch64ExpandPseudoPass(PassRegistry&);
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void initializeAArch64LoadStoreOptPass(PassRegistry&);
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void initializeAArch64SIMDInstrOptPass(PassRegistry&);
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void initializeAArch64PreLegalizerCombinerPass(PassRegistry&);
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void initializeAArch64PromoteConstantPass(PassRegistry&);
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void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
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void initializeAArch64StorePairSuppressPass(PassRegistry&);
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@ -0,0 +1,104 @@
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//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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namespace {
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class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
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public:
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AArch64PreLegalizerCombinerInfo()
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr) {}
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virtual bool combine(MachineInstr &MI, MachineIRBuilder &B) const override;
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};
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bool AArch64PreLegalizerCombinerInfo::combine(MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(B);
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switch (MI.getOpcode()) {
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default:
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return false;
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case TargetOpcode::G_ANYEXT:
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case TargetOpcode::G_SEXT:
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case TargetOpcode::G_ZEXT:
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return Helper.tryCombineExtendingLoads(MI);
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}
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return false;
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}
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// Pass boilerplate
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// ================
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class AArch64PreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PreLegalizerCombiner();
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StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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};
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}
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void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner() : MachineFunctionPass(ID) {
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initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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auto *TPC = &getAnalysis<TargetPassConfig>();
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AArch64PreLegalizerCombinerInfo PCInfo;
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Combiner C(PCInfo, TPC);
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return C.combineMachineInstrs(MF);
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}
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char AArch64PreLegalizerCombiner::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
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"Combine AArch64 machine instrs before legalization", false,
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false)
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namespace llvm {
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FunctionPass *createAArch64PreLegalizeCombiner() {
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return new AArch64PreLegalizerCombiner();
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}
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} // end namespace llvm
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@ -158,6 +158,7 @@ extern "C" void LLVMInitializeAArch64Target() {
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initializeAArch64ExpandPseudoPass(*PR);
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initializeAArch64LoadStoreOptPass(*PR);
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initializeAArch64SIMDInstrOptPass(*PR);
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initializeAArch64PreLegalizerCombinerPass(*PR);
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initializeAArch64PromoteConstantPass(*PR);
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initializeAArch64RedundantCopyEliminationPass(*PR);
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initializeAArch64StorePairSuppressPass(*PR);
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@ -338,6 +339,7 @@ public:
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addIRTranslator() override;
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void addPreLegalizeMachineIR() override;
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bool addLegalizeMachineIR() override;
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bool addRegBankSelect() override;
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void addPreGlobalInstructionSelect() override;
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@ -439,6 +441,10 @@ bool AArch64PassConfig::addIRTranslator() {
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return false;
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}
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void AArch64PassConfig::addPreLegalizeMachineIR() {
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addPass(createAArch64PreLegalizeCombiner());
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}
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bool AArch64PassConfig::addLegalizeMachineIR() {
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addPass(new Legalizer());
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return false;
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@ -43,6 +43,7 @@ add_llvm_target(AArch64CodeGen
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AArch64LoadStoreOptimizer.cpp
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AArch64MacroFusion.cpp
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AArch64MCInstLower.cpp
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AArch64PreLegalizerCombiner.cpp
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AArch64PromoteConstant.cpp
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AArch64PBQPRegAlloc.cpp
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AArch64RegisterBankInfo.cpp
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@ -65,7 +65,7 @@ false:
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s24) = G_LOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ZEXTLOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type_load
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; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type_load
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define i32 @odd_type_load() {
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@ -36,6 +36,7 @@
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; RUN: -debug-pass=Structure %s -o /dev/null 2>&1 | FileCheck %s --check-prefix DISABLED
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; ENABLED: IRTranslator
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; ENABLED-NEXT: PreLegalizerCombiner
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; ENABLED-NEXT: Legalizer
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; ENABLED-NEXT: RegBankSelect
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; ENABLED-O0-NEXT: Localizer
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@ -0,0 +1,25 @@
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# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_extload(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_extload
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_extload
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ANYEXT %1
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$w0 = COPY %2
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...
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@ -0,0 +1,45 @@
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# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_sextload(i8* %addr) {
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entry:
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ret void
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}
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define void @test_sextload_with_copy(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_sextload
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_sextload
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_SEXT %1
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$w0 = COPY %2
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...
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---
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name: test_sextload_with_copy
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_sextload_with_copy
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s8) = COPY %1
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%3:_(s32) = G_SEXT %2
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$w0 = COPY %3
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...
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@ -0,0 +1,25 @@
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# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_zextload(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_zextload
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: test_zextload
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; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[T1]](s32)
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%0:_(p0) = COPY $x0
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%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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%2:_(s32) = G_ZEXT %1
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$w0 = COPY %2
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...
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@ -33,6 +33,7 @@
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: IRTranslator
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; CHECK-NEXT: AArch64PreLegalizerCombiner
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; CHECK-NEXT: Legalizer
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; CHECK-NEXT: RegBankSelect
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; CHECK-NEXT: Localizer
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