[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
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Daniel Sanders
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602bff3184
commit
d240953db2
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@ -85,20 +85,34 @@ def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
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"Enable 'count leading bits' instructions.">;
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def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
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"Enable 'FP indexed load/store' instructions.">;
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips I ISA Support [highly experimental]">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips II ISA Support [highly experimental]",
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[FeatureMips1]>;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureCondMov, FeatureBitCount]>;
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[FeatureMips2, FeatureCondMov,
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FeatureBitCount]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips32, FeatureSEInReg, FeatureSwap,
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FeatureFPIdx]>;
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// FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
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// list but for now it doesn't matter since FPIdx isn't actually attached
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// to any instructions.
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureGP64Bit, FeatureFP64Bit]>;
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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[FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
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FeatureCondMov]>;
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[FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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[FeatureMips4]>;
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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[FeatureMips4, FeatureMips32, FeatureFPIdx]>;
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[FeatureMips5, FeatureMips32, FeatureFPIdx]>;
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def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
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"Mips64r2", "Mips64r2 ISA Support",
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[FeatureMips64, FeatureMips32r2]>;
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@ -126,9 +140,14 @@ def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
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def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
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def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
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def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
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def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
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def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
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def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
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def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
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def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
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def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
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@ -107,6 +107,19 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
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// MIPS-V. They have not been tested and currently exist for the integrated
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// assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips2)
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report_fatal_error("Code generation for MIPS-II is not implemented", false);
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if (MipsArchVersion == Mips3)
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report_fatal_error("Code generation for MIPS-III is not implemented",
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false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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// Assert exactly one ABI was chosen.
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assert(MipsABI != UnknownABI);
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assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
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@ -37,7 +37,8 @@ public:
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};
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protected:
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enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 };
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enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
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Mips64, Mips64r2 };
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// Mips architecture version
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MipsArchEnum MipsArchVersion;
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@ -2,8 +2,7 @@
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# FIXME: Test MIPS-I instead of MIPS32
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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@ -1,7 +1,6 @@
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# Instructions that are valid
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#
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# FIXME: Test MIPS-I instead of MIPS32
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
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.set noat
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abs.d $f7,$f25 # CHECK: encoding:
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@ -2,8 +2,7 @@
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# FIXME: Test MIPS-II instead of MIPS32
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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@ -1,7 +1,6 @@
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# Instructions that are valid
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#
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# FIXME: Test MIPS-II instead of MIPS32
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
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# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
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.set noat
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abs.d $f7,$f25 # CHECK: encoding
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@ -2,8 +2,7 @@
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# FIXME: Test MIPS-III instead of MIPS-IV
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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@ -1,7 +1,6 @@
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# Instructions that are valid
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#
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# FIXME: Test MIPS-III instead of MIPS-IV
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# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
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# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
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.set noat
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abs.d $f7,$f25 # CHECK: encoding
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@ -2,8 +2,7 @@
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# FIXME: Test MIPS-V instead of MIPS64
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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@ -1,7 +1,6 @@
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# Instructions that are valid
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#
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# FIXME: Test MIPS-V instead of MIPS64
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# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
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# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
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.set noat
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abs.d $f7,$f25 # CHECK: encoding
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