parent
ce400dac21
commit
d1f22b1282
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@ -1171,7 +1171,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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if (Opcode == ISD::SRA) {
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if (Opcode == ISD::SRA) {
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// If the sign bit is known to be zero, switch this to a SRL.
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// If the sign bit is known to be zero, switch this to a SRL.
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if (MaskedValueIsZero(N1,
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if (MaskedValueIsZero(N1,
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1ULL << MVT::getSizeInBits(N1.getValueType())-1,
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1ULL << (MVT::getSizeInBits(N1.getValueType())-1),
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TLI))
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TLI))
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return getNode(ISD::SRL, N1.getValueType(), N1, N2);
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return getNode(ISD::SRL, N1.getValueType(), N1, N2);
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} else {
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} else {
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