Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
llvm-svn: 146151
This commit is contained in:
parent
26edb291ac
commit
d19760a40c
|
@ -973,13 +973,14 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
SrcRegNum++;
|
||||
|
||||
// GAS sets the XOP_W even with register operands, we want to match this.
|
||||
// XOP_W is ignored, so there is no swapping of the operands
|
||||
XOP_W_I8IMMOperand = 3;
|
||||
if(HasXOP_W) // Skip 2nd src (which is encoded in I8IMM)
|
||||
SrcRegNum++;
|
||||
|
||||
EmitRegModRMByte(MI.getOperand(SrcRegNum),
|
||||
GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
|
||||
CurOp = SrcRegNum + 1;
|
||||
|
||||
// 2 operands skipped with HasXOP_W, comensate accordingly
|
||||
CurOp = HasXOP_W ? SrcRegNum : SrcRegNum + 1;
|
||||
if (HasVEX_4VOp3)
|
||||
++CurOp;
|
||||
break;
|
||||
|
@ -998,13 +999,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|||
|
||||
EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
|
||||
TSFlags, CurByte, OS, Fixups);
|
||||
if(HasXOP_W) {
|
||||
CurOp = NumOps - 1; // We have consumed all except one operand (third)
|
||||
} else {
|
||||
CurOp += AddrOperands + 1;
|
||||
if (HasVEX_4VOp3)
|
||||
++CurOp;
|
||||
}
|
||||
CurOp += AddrOperands + 1;
|
||||
if (HasVEX_4VOp3)
|
||||
++CurOp;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -68,7 +68,7 @@ multiclass fma4s<bits<8> opc, string OpcodeStr> {
|
|||
def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, XOP_W;
|
||||
def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
|
||||
|
@ -87,7 +87,7 @@ multiclass fma4p<bits<8> opc, string OpcodeStr> {
|
|||
def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, VR128:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, XOP_W;
|
||||
def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
|
||||
|
@ -102,7 +102,7 @@ multiclass fma4p<bits<8> opc, string OpcodeStr> {
|
|||
def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[]>, XOP_W;
|
||||
def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
|
||||
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
|
||||
|
|
Loading…
Reference in New Issue