[weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 195064

llvm/examples/ExceptionDemo/ExceptionDemo.cpp

@@ -1577,9 +1577,11 @@ public:
                                  std::runtime_error::operator=(toCopy)));
   }
 
-  ~OurCppRunException (void) throw () {}
+  ~OurCppRunException (void) throw ();
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+OurCppRunException::~OurCppRunException() throw () {}
 
 /// Throws foreign C++ exception.
 /// @param ignoreIt unused parameter that allows function to match implied

llvm/examples/Kaleidoscope/Chapter2/toy.cpp

@@ -79,13 +79,14 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
 };
 
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
 public:
   NumberExprAST(double val) {}
+  virtual ~NumberExprAST();
 };
 
 /// VariableExprAST - Expression class for referencing a variable, like "a".
@@ -93,12 +94,14 @@ class VariableExprAST : public ExprAST {
   std::string Name;
 public:
   VariableExprAST(const std::string &name) : Name(name) {}
+  virtual ~VariableExprAST();
 };
 
 /// BinaryExprAST - Expression class for a binary operator.
 class BinaryExprAST : public ExprAST {
 public:
   BinaryExprAST(char op, ExprAST *lhs, ExprAST *rhs) {}
+  virtual ~BinaryExprAST();
 };
 
 /// CallExprAST - Expression class for function calls.
@@ -108,8 +111,16 @@ class CallExprAST : public ExprAST {
 public:
   CallExprAST(const std::string &callee, std::vector<ExprAST*> &args)
     : Callee(callee), Args(args) {}
+  virtual ~CallExprAST();
 };
 
+// Provide out-of-line definitions to prevent weak vtables.
+ExprAST::~ExprAST() {}
+NumberExprAST::~NumberExprAST() {}
+VariableExprAST::~VariableExprAST() {}
+BinaryExprAST::~BinaryExprAST() {}
+CallExprAST::~CallExprAST() {}
+
 /// PrototypeAST - This class represents the "prototype" for a function,
 /// which captures its name, and its argument names (thus implicitly the number
 /// of arguments the function takes).

llvm/examples/Kaleidoscope/Chapter3/toy.cpp

@@ -84,10 +84,13 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
   virtual Value *Codegen() = 0;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+ExprAST::~ExprAST() {}
+
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
   double Val;

llvm/examples/Kaleidoscope/Chapter4/toy.cpp

@@ -91,10 +91,13 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
   virtual Value *Codegen() = 0;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+ExprAST::~ExprAST() {}
+
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
   double Val;

llvm/examples/Kaleidoscope/Chapter5/toy.cpp

@@ -100,10 +100,13 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
   virtual Value *Codegen() = 0;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+ExprAST::~ExprAST() {}
+
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
   double Val;

llvm/examples/Kaleidoscope/Chapter6/toy.cpp

@@ -105,10 +105,13 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
   virtual Value *Codegen() = 0;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+ExprAST::~ExprAST() {}
+
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
   double Val;

llvm/examples/Kaleidoscope/Chapter7/toy.cpp

@@ -109,10 +109,13 @@ static int gettok() {
 /// ExprAST - Base class for all expression nodes.
 class ExprAST {
 public:
-  virtual ~ExprAST() {}
+  virtual ~ExprAST();
   virtual Value *Codegen() = 0;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+ExprAST::~ExprAST() {}
+
 /// NumberExprAST - Expression class for numeric literals like "1.0".
 class NumberExprAST : public ExprAST {
   double Val;

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

@@ -30,8 +30,9 @@ class PSetIterator;
 class MachineRegisterInfo {
 public:
   class Delegate {
+    virtual void anchor();
   public:
-    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) {}
+    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
 
     virtual ~Delegate() {}
   };

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -164,6 +164,7 @@ struct MachineSchedPolicy {
 /// Initialization sequence:
 ///   initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
 class MachineSchedStrategy {
+  virtual void anchor();
 public:
   virtual ~MachineSchedStrategy() {}
 
@@ -262,6 +263,7 @@ public:
 
 /// Mutate the DAG as a postpass after normal DAG building.
 class ScheduleDAGMutation {
+  virtual void anchor();
 public:
   virtual ~ScheduleDAGMutation() {}
 

llvm/include/llvm/ExecutionEngine/ObjectBuffer.h

@@ -30,6 +30,7 @@ namespace llvm {
 /// ObjectFile) as needed, but the MemoryBuffer instance returned does not own the
 /// actual memory it points to.
 class ObjectBuffer {
+  virtual void anchor();
 public:
   ObjectBuffer() {}
   ObjectBuffer(MemoryBuffer* Buf) : Buffer(Buf) {}
@@ -56,6 +57,7 @@ protected:
 /// while providing a common ObjectBuffer interface for access to the
 /// memory once the object has been generated.
 class ObjectBufferStream : public ObjectBuffer {
+  virtual void anchor();
 public:
   ObjectBufferStream() : OS(SV) {}
   virtual ~ObjectBufferStream() {}

llvm/include/llvm/ExecutionEngine/ObjectCache.h

@@ -20,6 +20,7 @@ class Module;
 /// ExecutionEngine for the purpose of avoiding compilation for Modules that
 /// have already been compiled and an object file is available.
 class ObjectCache {
+  virtual void anchor();
 public:
   ObjectCache() { }
 

llvm/include/llvm/ExecutionEngine/ObjectImage.h

@@ -25,6 +25,7 @@ namespace llvm {
 class ObjectImage {
   ObjectImage() LLVM_DELETED_FUNCTION;
   ObjectImage(const ObjectImage &other) LLVM_DELETED_FUNCTION;
+  virtual void anchor();
 
 protected:
   OwningPtr<ObjectBuffer> Buffer;

llvm/include/llvm/MC/MCAtom.h

@@ -32,6 +32,7 @@ class MCDataAtom;
 /// \brief Represents a contiguous range of either instructions (a TextAtom)
 /// or data (a DataAtom).  Address ranges are expressed as _closed_ intervals.
 class MCAtom {
+  virtual void anchor();
 public:
   virtual ~MCAtom() {}
 

llvm/include/llvm/MC/MCStreamer.h

@@ -76,6 +76,7 @@ public:
 // FIXME: declared here because it is used from
 // lib/CodeGen/AsmPrinter/ARMException.cpp.
 class ARMTargetStreamer : public MCTargetStreamer {
+  virtual void anchor();
 public:
   virtual void emitFnStart() = 0;
   virtual void emitFnEnd() = 0;

llvm/include/llvm/MC/MCWinCOFFObjectWriter.h

@@ -17,6 +17,7 @@ namespace llvm {
   class raw_ostream;
 
   class MCWinCOFFObjectTargetWriter {
+    virtual void anchor();
     const unsigned Machine;
 
   protected:

llvm/include/llvm/Support/CommandLine.h

@@ -350,6 +350,9 @@ struct cat {
 struct GenericOptionValue {
   virtual ~GenericOptionValue() {}
   virtual bool compare(const GenericOptionValue &V) const = 0;
+
+private:
+  virtual void anchor();
 };
 
 template<class DataType> struct OptionValue;
@@ -1752,6 +1755,7 @@ void getRegisteredOptions(StringMap<Option*> &Map);
 /// \brief Saves strings in the inheritor's stable storage and returns a stable
 /// raw character pointer.
 class StringSaver {
+  virtual void anchor();
 public:
   virtual const char *SaveString(const char *Str) = 0;
   virtual ~StringSaver() {};  // Pacify -Wnon-virtual-dtor.

llvm/include/llvm/Support/ValueHandle.h

@@ -339,6 +339,7 @@ public:
 /// rearrange itself when the pointer changes).  Unlike ValueHandleBase, this
 /// class has a vtable and a virtual destructor.
 class CallbackVH : public ValueHandleBase {
+  virtual void anchor();
 protected:
   CallbackVH(const CallbackVH &RHS)
     : ValueHandleBase(Callback, RHS) {}
@@ -365,13 +366,13 @@ public:
   ///
   /// All implementations must remove the reference from this object to the
   /// Value that's being destroyed.
-  virtual void deleted();
+  virtual void deleted() { setValPtr(NULL); }
 
   /// Called when this->getValPtr()->replaceAllUsesWith(new_value) is called,
   /// _before_ any of the uses have actually been replaced.  If WeakVH were
   /// implemented as a CallbackVH, it would use this method to call
   /// setValPtr(new_value).  AssertingVH would do nothing in this method.
-  virtual void allUsesReplacedWith(Value *);
+  virtual void allUsesReplacedWith(Value *) {}
 };
 
 } // End llvm namespace

llvm/include/llvm/Support/YAMLParser.h

@@ -105,6 +105,7 @@ private:
 
 /// @brief Abstract base class for all Nodes.
 class Node {
+   virtual void anchor();
 public:
   enum NodeKind {
     NK_Null,
@@ -175,6 +176,7 @@ private:
 /// Example:
 ///   !!null null
 class NullNode : public Node {
+  virtual void anchor();
 public:
   NullNode(OwningPtr<Document> &D)
       : Node(NK_Null, D, StringRef(), StringRef()) {}
@@ -190,6 +192,7 @@ public:
 /// Example:
 ///   Adena
 class ScalarNode : public Node {
+  virtual void anchor();
 public:
   ScalarNode(OwningPtr<Document> &D, StringRef Anchor, StringRef Tag,
              StringRef Val)
@@ -231,6 +234,7 @@ private:
 /// Example:
 ///   Section: .text
 class KeyValueNode : public Node {
+  virtual void anchor();
 public:
   KeyValueNode(OwningPtr<Document> &D)
     : Node(NK_KeyValue, D, StringRef(), StringRef())
@@ -342,6 +346,7 @@ void skip(CollectionType &C) {
 ///   Name: _main
 ///   Scope: Global
 class MappingNode : public Node {
+  virtual void anchor();
 public:
   enum MappingType {
     MT_Block,
@@ -391,6 +396,7 @@ private:
 ///   - Hello
 ///   - World
 class SequenceNode : public Node {
+  virtual void anchor();
 public:
   enum SequenceType {
     ST_Block,
@@ -446,6 +452,7 @@ private:
 /// Example:
 ///   *AnchorName
 class AliasNode : public Node {
+  virtual void anchor();
 public:
   AliasNode(OwningPtr<Document> &D, StringRef Val)
     : Node(NK_Alias, D, StringRef(), StringRef()), Name(Val) {}

llvm/include/llvm/Support/YAMLTraits.h

@@ -725,6 +725,7 @@ private:
   virtual bool canElideEmptySequence();
 
   class HNode {
+    virtual void anchor();
   public:
     HNode(Node *n) : _node(n) { }
     virtual ~HNode() { }
@@ -734,9 +735,9 @@ private:
   };
 
   class EmptyHNode : public HNode {
+    virtual void anchor();
   public:
     EmptyHNode(Node *n) : HNode(n) { }
-    virtual ~EmptyHNode() {}
     static inline bool classof(const HNode *n) {
       return NullNode::classof(n->_node);
     }
@@ -744,9 +745,9 @@ private:
   };
 
   class ScalarHNode : public HNode {
+    virtual void anchor();
   public:
     ScalarHNode(Node *n, StringRef s) : HNode(n), _value(s) { }
-    virtual ~ScalarHNode() { }
 
     StringRef value() const { return _value; }
 

llvm/lib/CodeGen/MachineRegisterInfo.cpp

@@ -19,6 +19,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void MachineRegisterInfo::Delegate::anchor() {}
+
 MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
   : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) {
   VRegInfo.reserve(256);

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -72,6 +72,10 @@ static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
 // DAG subtrees must have at least this many nodes.
 static const unsigned MinSubtreeSize = 8;
 
+// Pin the vtables to this file.
+void MachineSchedStrategy::anchor() {}
+void ScheduleDAGMutation::anchor() {}
+
 //===----------------------------------------------------------------------===//
 // Machine Instruction Scheduling Pass and Registry
 //===----------------------------------------------------------------------===//

llvm/lib/CodeGen/RegAllocBase.cpp

@@ -50,6 +50,9 @@ bool RegAllocBase::VerifyEnabled = false;
 //                         RegAllocBase Implementation
 //===----------------------------------------------------------------------===//
 
+// Pin the vtable to this file.
+void RegAllocBase::anchor() {}
+
 void RegAllocBase::init(VirtRegMap &vrm,
                         LiveIntervals &lis,
                         LiveRegMatrix &mat) {

llvm/lib/CodeGen/RegAllocBase.h

@@ -57,6 +57,7 @@ class Spiller;
 /// live range splitting. They must also override enqueue/dequeue to provide an
 /// assignment order.
 class RegAllocBase {
+  virtual void anchor();
 protected:
   const TargetRegisterInfo *TRI;
   MachineRegisterInfo *MRI;

llvm/lib/ExecutionEngine/ExecutionEngine.cpp

@@ -15,6 +15,7 @@
 #define DEBUG_TYPE "jit"
 #include "llvm/ExecutionEngine/ExecutionEngine.h"
 #include "llvm/ExecutionEngine/JITMemoryManager.h"
+#include "llvm/ExecutionEngine/ObjectCache.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
@@ -39,6 +40,11 @@ using namespace llvm;
 STATISTIC(NumInitBytes, "Number of bytes of global vars initialized");
 STATISTIC(NumGlobals  , "Number of global vars initialized");
 
+// Pin the vtable to this file.
+void ObjectCache::anchor() {}
+void ObjectBuffer::anchor() {}
+void ObjectBufferStream::anchor() {}
+
 ExecutionEngine *(*ExecutionEngine::JITCtor)(
   Module *M,
   std::string *ErrorStr,

llvm/lib/ExecutionEngine/RuntimeDyld/JITRegistrar.h

@@ -16,6 +16,7 @@ namespace llvm {
 
 /// Global access point for the JIT debugging interface.
 class JITRegistrar {
+  virtual void anchor();
 public:
   /// Instantiates the JIT service.
   JITRegistrar() {}

llvm/lib/ExecutionEngine/RuntimeDyld/ObjectImageCommon.h

@@ -23,6 +23,7 @@ namespace llvm {
 class ObjectImageCommon : public ObjectImage {
   ObjectImageCommon(); // = delete
   ObjectImageCommon(const ObjectImageCommon &other); // = delete
+  virtual void anchor();
 
 protected:
   object::ObjectFile *ObjFile;

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp

@@ -13,6 +13,7 @@
 
 #define DEBUG_TYPE "dyld"
 #include "llvm/ExecutionEngine/RuntimeDyld.h"
+#include "JITRegistrar.h"
 #include "ObjectImageCommon.h"
 #include "RuntimeDyldELF.h"
 #include "RuntimeDyldImpl.h"
@@ -28,6 +29,11 @@ using namespace llvm::object;
 // Empty out-of-line virtual destructor as the key function.
 RuntimeDyldImpl::~RuntimeDyldImpl() {}
 
+// Pin the JITRegistrar's and ObjectImage*'s vtables to this file.
+void JITRegistrar::anchor() {}
+void ObjectImage::anchor() {}
+void ObjectImageCommon::anchor() {}
+
 namespace llvm {
 
 void RuntimeDyldImpl::registerEHFrames() {

llvm/lib/IR/AttributeImpl.h

@@ -94,6 +94,7 @@ public:
 /// attribute enties, which are for target-dependent attributes.
 
 class EnumAttributeImpl : public AttributeImpl {
+  virtual void anchor();
   Attribute::AttrKind Kind;
 
 protected:
@@ -108,6 +109,7 @@ public:
 };
 
 class AlignAttributeImpl : public EnumAttributeImpl {
+  virtual void anchor();
   unsigned Align;
 
 public:
@@ -122,6 +124,7 @@ public:
 };
 
 class StringAttributeImpl : public AttributeImpl {
+  virtual void anchor();
   std::string Kind;
   std::string Val;
 

llvm/lib/IR/Attributes.cpp

@@ -286,7 +286,11 @@ bool Attribute::operator<(Attribute A) const {
 // AttributeImpl Definition
 //===----------------------------------------------------------------------===//
 
+// Pin the vtabels to this file.
 AttributeImpl::~AttributeImpl() {}
+void EnumAttributeImpl::anchor() {}
+void AlignAttributeImpl::anchor() {}
+void StringAttributeImpl::anchor() {}
 
 bool AttributeImpl::hasAttribute(Attribute::AttrKind A) const {
   if (isStringAttribute()) return false;

llvm/lib/IR/Metadata.cpp

@@ -65,7 +65,7 @@ class MDNodeOperand : public CallbackVH {
 
 public:
   MDNodeOperand(Value *V) : CallbackVH(V) {}
-  ~MDNodeOperand() {}
+  virtual ~MDNodeOperand();
 
   void set(Value *V) {
     unsigned IsFirst = this->getValPtrInt();
@@ -82,6 +82,8 @@ public:
 };
 } // end namespace llvm.
 
+// Provide out-of-line definition to prevent weak vtable.
+MDNodeOperand::~MDNodeOperand() {}
 
 void MDNodeOperand::deleted() {
   getParent()->replaceOperand(this, 0);

llvm/lib/IR/Value.cpp

@@ -735,9 +735,5 @@ void ValueHandleBase::ValueIsRAUWd(Value *Old, Value *New) {
 #endif
 }
 
-// Default implementation for CallbackVH.
-void CallbackVH::allUsesReplacedWith(Value *) {}
-
-void CallbackVH::deleted() {
-  setValPtr(NULL);
-}
+// Pin the vtable to this file.
+void CallbackVH::anchor() {}

llvm/lib/MC/MCAtom.cpp

@@ -14,6 +14,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void MCAtom::anchor() {}
+
 void MCAtom::remap(uint64_t NewBegin, uint64_t NewEnd) {
   Parent->remap(this, NewBegin, NewEnd);
 }

llvm/lib/MC/MCStreamer.cpp

@@ -22,7 +22,9 @@
 #include <cstdlib>
 using namespace llvm;
 
+// Pin the vtables to this file.
 MCTargetStreamer::~MCTargetStreamer() {}
+void ARMTargetStreamer::anchor() {}
 
 MCStreamer::MCStreamer(MCContext &Ctx, MCTargetStreamer *TargetStreamer)
     : Context(Ctx), TargetStreamer(TargetStreamer), EmitEHFrame(true),

llvm/lib/MC/WinCOFFObjectWriter.cpp

@@ -138,7 +138,7 @@ public:
   symbol_map  SymbolMap;
 
   WinCOFFObjectWriter(MCWinCOFFObjectTargetWriter *MOTW, raw_ostream &OS);
-  ~WinCOFFObjectWriter();
+  virtual ~WinCOFFObjectWriter();
 
   COFFSymbol *createSymbol(StringRef Name);
   COFFSymbol *GetOrCreateCOFFSymbol(const MCSymbol * Symbol);
@@ -915,6 +915,9 @@ MCWinCOFFObjectTargetWriter::MCWinCOFFObjectTargetWriter(unsigned Machine_) :
   Machine(Machine_) {
 }
 
+// Pin the vtable to this file.
+void MCWinCOFFObjectTargetWriter::anchor() {}
+
 //------------------------------------------------------------------------------
 // WinCOFFObjectWriter factory function
 

llvm/lib/Support/CommandLine.cpp

@@ -60,6 +60,8 @@ TEMPLATE_INSTANTIATION(class opt<char>);
 TEMPLATE_INSTANTIATION(class opt<bool>);
 } } // end namespace llvm::cl
 
+// Pin the vtables to this file.
+void GenericOptionValue::anchor() {}
 void OptionValue<boolOrDefault>::anchor() {}
 void OptionValue<std::string>::anchor() {}
 void Option::anchor() {}
@@ -73,6 +75,7 @@ void parser<double>::anchor() {}
 void parser<float>::anchor() {}
 void parser<std::string>::anchor() {}
 void parser<char>::anchor() {}
+void StringSaver::anchor() {}
 
 //===----------------------------------------------------------------------===//
 

llvm/lib/Support/YAMLParser.cpp

@@ -96,6 +96,15 @@ static EncodingInfo getUnicodeEncoding(StringRef Input) {
 
 namespace llvm {
 namespace yaml {
+/// Pin the vtables to this file.
+void Node::anchor() {}
+void NullNode::anchor() {}
+void ScalarNode::anchor() {}
+void KeyValueNode::anchor() {}
+void MappingNode::anchor() {}
+void SequenceNode::anchor() {}
+void AliasNode::anchor() {}
+
 /// Token - A single YAML token.
 struct Token : ilist_node<Token> {
   enum TokenKind {

llvm/lib/Support/YAMLTraits.cpp

@@ -60,6 +60,11 @@ error_code Input::error() {
   return EC;
 }
 
+// Pin the vtables to this file.
+void Input::HNode::anchor() {}
+void Input::EmptyHNode::anchor() {}
+void Input::ScalarHNode::anchor() {}
+
 bool Input::outputting() const {
   return false;
 }

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -29,7 +29,7 @@
 
 #include <algorithm>
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "AArch64GenInstrInfo.inc"
 
 using namespace llvm;

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

@@ -25,6 +25,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void AArch64Subtarget::anchor() {}
+
 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS)
     : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false),
       HasCrypto(false), TargetTriple(TT), CPUString(CPU) {

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -27,6 +27,7 @@ class StringRef;
 class GlobalValue;
 
 class AArch64Subtarget : public AArch64GenSubtargetInfo {
+  virtual void anchor();
 protected:
   bool HasFPARMv8;
   bool HasNEON;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

@@ -37,3 +37,6 @@ AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() {
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
 }
+
+// Pin the vtable to this file.
+void AArch64ELFMCAsmInfo::anchor() {}

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h

@@ -18,9 +18,11 @@
 
 namespace llvm {
 
-  struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
-    explicit AArch64ELFMCAsmInfo();
-  };
+struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
+  explicit AArch64ELFMCAsmInfo();
+private:
+  virtual void anchor();
+};
 
 } // namespace llvm
 

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

@@ -37,7 +37,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "ARMGenInstrInfo.inc"
 
 using namespace llvm;

llvm/lib/Target/Hexagon/CMakeLists.txt

@@ -17,6 +17,7 @@ add_llvm_target(HexagonCodeGen
   HexagonFrameLowering.cpp
   HexagonHardwareLoops.cpp
   HexagonFixupHwLoops.cpp
+  HexagonMachineFunctionInfo.cpp
   HexagonMachineScheduler.cpp
   HexagonMCInstLower.cpp
   HexagonInstrInfo.cpp

llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

@@ -26,7 +26,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #define GET_INSTRMAP_INFO
 #include "HexagonGenInstrInfo.inc"
 #include "HexagonGenDFAPacketizer.inc"
@@ -55,6 +55,8 @@ const int Hexagon_MEMH_AUTOINC_MIN = -16;
 const int Hexagon_MEMB_AUTOINC_MAX = 7;
 const int Hexagon_MEMB_AUTOINC_MIN = -8;
 
+// Pin the vtable to this file.
+void HexagonInstrInfo::anchor() {}
 
 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
   : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),

llvm/lib/Target/Hexagon/HexagonInstrInfo.h

@@ -26,6 +26,7 @@
 namespace llvm {
 
 class HexagonInstrInfo : public HexagonGenInstrInfo {
+  virtual void anchor();
   const HexagonRegisterInfo RI;
   const HexagonSubtarget &Subtarget;
   typedef unsigned Opcode_t;

llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp

@@ -0,0 +1,16 @@
+//= HexagonMachineFunctionInfo.cpp - Hexagon machine function info *- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "HexagonMachineFunctionInfo.h"
+
+using namespace llvm;
+
+// pin vtable to this file
+void HexagonMachineFunctionInfo::anchor() {}
+

llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h

@@ -1,4 +1,4 @@
-//=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=//
+//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -10,6 +10,7 @@
 #ifndef HexagonMACHINEFUNCTIONINFO_H
 #define HexagonMACHINEFUNCTIONINFO_H
 
+#include <map>
 #include "llvm/CodeGen/MachineFunction.h"
 
 namespace llvm {
@@ -30,9 +31,8 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo {
   int VarArgsFrameIndex;
   bool HasClobberLR;
   bool HasEHReturn;
-
   std::map<const MachineInstr*, unsigned> PacketInfo;
-
+  virtual void anchor();
 
 public:
   HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),

llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

@@ -86,3 +86,5 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
     ModeIEEERndNear = false;
 }
 
+// Pin the vtable to this file.
+void HexagonSubtarget::anchor() {}

llvm/lib/Target/Hexagon/HexagonSubtarget.h

@@ -27,7 +27,7 @@
 namespace llvm {
 
 class HexagonSubtarget : public HexagonGenSubtargetInfo {
-
+  virtual void anchor();
   bool UseMemOps;
   bool ModeIEEERndNear;
 

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

@@ -15,6 +15,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void HexagonMCAsmInfo::anchor() {}
+
 HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) {
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h

@@ -19,6 +19,7 @@
 
 namespace llvm {
   class HexagonMCAsmInfo : public MCAsmInfoELF {
+    virtual void anchor();
   public:
     explicit HexagonMCAsmInfo(StringRef TT);
   };

llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

@@ -22,11 +22,14 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "MSP430GenInstrInfo.inc"
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void MSP430InstrInfo::anchor() {}
+
 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
   : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
     RI(tm) {}

llvm/lib/Target/MSP430/MSP430InstrInfo.h

@@ -42,6 +42,7 @@ namespace MSP430II {
 
 class MSP430InstrInfo : public MSP430GenInstrInfo {
   const MSP430RegisterInfo RI;
+  virtual void anchor();
 public:
   explicit MSP430InstrInfo(MSP430TargetMachine &TM);
 

llvm/lib/Target/Mips/MipsInstrInfo.cpp

@@ -22,11 +22,14 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "MipsGenInstrInfo.inc"
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void MipsInstrInfo::anchor() {}
+
 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
   : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     TM(tm), UncondBrOpc(UncondBr) {}

llvm/lib/Target/Mips/MipsInstrInfo.h

@@ -27,6 +27,7 @@
 namespace llvm {
 
 class MipsInstrInfo : public MipsGenInstrInfo {
+  virtual void anchor();
 protected:
   MipsTargetMachine &TM;
   unsigned UncondBrOpc;

llvm/lib/Target/Mips/MipsTargetStreamer.h

@@ -16,7 +16,6 @@
 namespace llvm {
 class MipsTargetStreamer : public MCTargetStreamer {
   virtual void anchor();
-
 public:
   virtual void emitMipsHackELFFlags(unsigned Flags) = 0;
   virtual void emitMipsHackSTOCG(MCSymbol *Sym, unsigned Val) = 0;

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -2288,3 +2288,29 @@ void NVPTXTargetLowering::ReplaceNodeResults(
     return;
   }
 }
+
+// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
+void NVPTXSection::anchor() {}
+
+NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
+  delete TextSection;
+  delete DataSection;
+  delete BSSSection;
+  delete ReadOnlySection;
+
+  delete StaticCtorSection;
+  delete StaticDtorSection;
+  delete LSDASection;
+  delete EHFrameSection;
+  delete DwarfAbbrevSection;
+  delete DwarfInfoSection;
+  delete DwarfLineSection;
+  delete DwarfFrameSection;
+  delete DwarfPubTypesSection;
+  delete DwarfDebugInlineSection;
+  delete DwarfStrSection;
+  delete DwarfLocSection;
+  delete DwarfARangesSection;
+  delete DwarfRangesSection;
+  delete DwarfMacroInfoSection;
+}

llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp

@@ -14,7 +14,7 @@
 #include "NVPTX.h"
 #include "NVPTXInstrInfo.h"
 #include "NVPTXTargetMachine.h"
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "NVPTXGenInstrInfo.inc"
 #include "llvm/IR/Function.h"
 #include "llvm/ADT/STLExtras.h"
@@ -24,6 +24,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+void NVPTXInstrInfo::anchor() {}
+
 // FIXME: Add the subtarget support on this constructor.
 NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm)
     : NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {}

llvm/lib/Target/NVPTX/NVPTXInstrInfo.h

@@ -26,6 +26,7 @@ namespace llvm {
 class NVPTXInstrInfo : public NVPTXGenInstrInfo {
   NVPTXTargetMachine &TM;
   const NVPTXRegisterInfo RegInfo;
+  virtual void anchor();
 public:
   explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
 

llvm/lib/Target/NVPTX/NVPTXSection.h

@@ -24,10 +24,10 @@ namespace llvm {
 /// the ASMPrint interface.
 ///
 class NVPTXSection : public MCSection {
-
+  virtual void anchor();
 public:
   NVPTXSection(SectionVariant V, SectionKind K) : MCSection(V, K) {}
-  ~NVPTXSection() {}
+  virtual ~NVPTXSection() {}
 
   /// Override this as NVPTX has its own way of printing switching
   /// to a section.

llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp

@@ -20,6 +20,9 @@
 using namespace llvm;
 
 
+// Pin the vtable to this file.
+void NVPTXSubtarget::anchor() {}
+
 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
                                const std::string &FS, bool is64Bit)
     : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),

llvm/lib/Target/NVPTX/NVPTXSubtarget.h

@@ -25,7 +25,7 @@
 namespace llvm {
 
 class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
-
+  virtual void anchor();
   std::string TargetName;
   NVPTX::DrvInterface drvInterface;
   bool Is64Bit;

llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h

@@ -44,28 +44,7 @@ public:
     DwarfMacroInfoSection = 0;
   }
 
-  ~NVPTXTargetObjectFile() {
-    delete TextSection;
-    delete DataSection;
-    delete BSSSection;
-    delete ReadOnlySection;
-
-    delete StaticCtorSection;
-    delete StaticDtorSection;
-    delete LSDASection;
-    delete EHFrameSection;
-    delete DwarfAbbrevSection;
-    delete DwarfInfoSection;
-    delete DwarfLineSection;
-    delete DwarfFrameSection;
-    delete DwarfPubTypesSection;
-    delete DwarfDebugInlineSection;
-    delete DwarfStrSection;
-    delete DwarfLocSection;
-    delete DwarfARangesSection;
-    delete DwarfRangesSection;
-    delete DwarfMacroInfoSection;
-  }
+  virtual ~NVPTXTargetObjectFile();
 
   virtual void Initialize(MCContext &ctx, const TargetMachine &TM) {
     TargetLoweringObjectFile::Initialize(ctx, TM);

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

@@ -37,6 +37,9 @@
 
 using namespace llvm;
 
+// Pin the vtable to this file.
+PPCTargetStreamer::~PPCTargetStreamer() {}
+
 static MCInstrInfo *createPPCMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitPPCMCInstrInfo(X);

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -33,7 +33,7 @@
 #include "llvm/Support/raw_ostream.h"
 
 #define GET_INSTRMAP_INFO
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "PPCGenInstrInfo.inc"
 
 using namespace llvm;
@@ -45,6 +45,9 @@ opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
 cl::desc("Disable compare instruction optimization"), cl::Hidden);
 
+// Pin the vtable to this file.
+void PPCInstrInfo::anchor() {}
+
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     TM(tm), RI(*TM.getSubtargetImpl()) {}

llvm/lib/Target/PowerPC/PPCInstrInfo.h

@@ -78,6 +78,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
                             const TargetRegisterClass *RC,
                             SmallVectorImpl<MachineInstr*> &NewMIs,
                             bool &NonRI, bool &SpillsVRS) const;
+  virtual void anchor();
 public:
   explicit PPCInstrInfo(PPCTargetMachine &TM);
 

llvm/lib/Target/PowerPC/PPCTargetStreamer.h

@@ -15,6 +15,7 @@
 namespace llvm {
 class PPCTargetStreamer : public MCTargetStreamer {
 public:
+  virtual ~PPCTargetStreamer();
   virtual void emitTCEntry(const MCSymbol &S) = 0;
 };
 }

llvm/lib/Target/R600/AMDGPUInstrInfo.cpp

@@ -20,13 +20,17 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #define GET_INSTRINFO_NAMED_OPS
 #define GET_INSTRMAP_INFO
 #include "AMDGPUGenInstrInfo.inc"
 
 using namespace llvm;
 
+
+// Pin the vtable to this file.
+void AMDGPUInstrInfo::anchor() {}
+
 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
   : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { }
 

llvm/lib/Target/R600/AMDGPUInstrInfo.h

@@ -43,6 +43,7 @@ private:
   const AMDGPURegisterInfo RI;
   bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
                           MachineBasicBlock &MBB) const;
+  virtual void anchor();
 protected:
   TargetMachine &TM;
 public:

llvm/lib/Target/R600/AMDGPUMachineFunction.cpp

@@ -6,6 +6,9 @@ using namespace llvm;
 
 static const char *const ShaderTypeAttribute = "ShaderType";
 
+// Pin the vtable to this file.
+void AMDGPUMachineFunction::anchor() {}
+
 AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) :
     MachineFunctionInfo() {
   ShaderType = ShaderType::COMPUTE;

llvm/lib/Target/R600/AMDGPUMachineFunction.h

@@ -19,6 +19,7 @@
 namespace llvm {
 
 class AMDGPUMachineFunction : public MachineFunctionInfo {
+  virtual void anchor();
 public:
   AMDGPUMachineFunction(const MachineFunction &MF);
   unsigned ShaderType;

llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

@@ -0,0 +1,21 @@
+//===-- AMDGPUCodeEmitter.cpp - AMDGPU Code Emitter interface -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// \brief CodeEmitter interface for R600 and SI codegen.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUMCCodeEmitter.h"
+
+using namespace llvm;
+
+// pin vtable to this file
+void AMDGPUMCCodeEmitter::anchor() {}
+

llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h

@@ -24,6 +24,7 @@ class MCInst;
 class MCOperand;
 
 class AMDGPUMCCodeEmitter : public MCCodeEmitter {
+  virtual void anchor();
 public:
 
   uint64_t getBinaryCodeForInstr(const MCInst &MI,

llvm/lib/Target/R600/MCTargetDesc/CMakeLists.txt

@@ -2,6 +2,7 @@
 add_llvm_library(LLVMR600Desc
   AMDGPUAsmBackend.cpp
   AMDGPUELFObjectWriter.cpp
+  AMDGPUMCCodeEmitter.cpp
   AMDGPUMCTargetDesc.cpp
   AMDGPUMCAsmInfo.cpp
   R600MCCodeEmitter.cpp

llvm/lib/Target/R600/R600InstrInfo.cpp

@@ -23,7 +23,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "AMDGPUGenDFAPacketizer.inc"
 
 using namespace llvm;

llvm/lib/Target/R600/R600MachineFunctionInfo.cpp

@@ -12,7 +12,9 @@
 
 using namespace llvm;
 
+
+// Pin the vtable to this file.
+void R600MachineFunctionInfo::anchor() {}
+
 R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
   : AMDGPUMachineFunction(MF) { }
-
-

llvm/lib/Target/R600/R600MachineFunctionInfo.h

@@ -21,6 +21,7 @@
 namespace llvm {
 
 class R600MachineFunctionInfo : public AMDGPUMachineFunction {
+  virtual void anchor();
 public:
   R600MachineFunctionInfo(const MachineFunction &MF);
   SmallVector<unsigned, 4> LiveOuts;

llvm/lib/Target/R600/SIMachineFunctionInfo.cpp

@@ -13,6 +13,10 @@
 
 using namespace llvm;
 
+
+// Pin the vtable to this file.
+void SIMachineFunctionInfo::anchor() {}
+
 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
   : AMDGPUMachineFunction(MF),
     PSInputAddr(0) { }

llvm/lib/Target/R600/SIMachineFunctionInfo.h

@@ -22,6 +22,7 @@ namespace llvm {
 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
 /// tells the hardware which interpolation parameters to load.
 class SIMachineFunctionInfo : public AMDGPUMachineFunction {
+  virtual void anchor();
 public:
   SIMachineFunctionInfo(const MachineFunction &MF);
   unsigned PSInputAddr;

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

@@ -24,11 +24,15 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "SparcGenInstrInfo.inc"
 
 using namespace llvm;
 
+
+// Pin the vtable to this file.
+void SparcInstrInfo::anchor() {}
+
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
   : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     RI(ST), Subtarget(ST) {

llvm/lib/Target/Sparc/SparcInstrInfo.h

@@ -37,6 +37,7 @@ namespace SPII {
 class SparcInstrInfo : public SparcGenInstrInfo {
   const SparcRegisterInfo RI;
   const SparcSubtarget& Subtarget;
+  virtual void anchor();
 public:
   explicit SparcInstrInfo(SparcSubtarget &ST);
 

llvm/lib/Target/SystemZ/CMakeLists.txt

@@ -21,6 +21,7 @@ add_llvm_target(SystemZCodeGen
   SystemZISelLowering.cpp
   SystemZInstrInfo.cpp
   SystemZLongBranch.cpp
+  SystemZMachineFunctionInfo.cpp
   SystemZMCInstLower.cpp
   SystemZRegisterInfo.cpp
   SystemZSelectionDAGInfo.cpp

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

@@ -17,7 +17,7 @@
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #define GET_INSTRMAP_INFO
 #include "SystemZGenInstrInfo.inc"
 
@@ -37,6 +37,9 @@ static bool isHighReg(unsigned int Reg) {
   return false;
 }
 
+// Pin the vtable to this file.
+void SystemZInstrInfo::anchor() {}
+
 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
   : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
     RI(tm), TM(tm) {

llvm/lib/Target/SystemZ/SystemZInstrInfo.h

@@ -127,6 +127,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
   void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      DebugLoc DL, unsigned DestReg, unsigned SrcReg,
                      unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
+  virtual void anchor();
   
 public:
   explicit SystemZInstrInfo(SystemZTargetMachine &TM);

llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp

@@ -0,0 +1,17 @@
+//== SystemZMachineFuctionInfo.cpp - SystemZ machine function info-*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "SystemZMachineFunctionInfo.h"
+
+using namespace llvm;
+
+
+// pin vtable to this file
+void SystemZMachineFunctionInfo::anchor() {}
+

llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h

@@ -15,6 +15,7 @@
 namespace llvm {
 
 class SystemZMachineFunctionInfo : public MachineFunctionInfo {
+  virtual void anchor();
   unsigned LowSavedGPR;
   unsigned HighSavedGPR;
   unsigned VarArgsFirstGPR;

llvm/lib/Target/SystemZ/SystemZSubtarget.cpp

@@ -18,6 +18,9 @@
 
 using namespace llvm;
 
+// Pin the vtabel to this file.
+void SystemZSubtarget::anchor() {}
+
 SystemZSubtarget::SystemZSubtarget(const std::string &TT,
                                    const std::string &CPU,
                                    const std::string &FS)

llvm/lib/Target/SystemZ/SystemZSubtarget.h

@@ -26,6 +26,7 @@ class GlobalValue;
 class StringRef;
 
 class SystemZSubtarget : public SystemZGenSubtargetInfo {
+  virtual void anchor();
 protected:
   bool HasDistinctOps;
   bool HasLoadStoreOnCond;

llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp

@@ -27,7 +27,7 @@ namespace {
 
   public:
     X86WinCOFFObjectWriter(bool Is64Bit_);
-    ~X86WinCOFFObjectWriter();
+    virtual ~X86WinCOFFObjectWriter();
 
     virtual unsigned getRelocType(const MCValue &Target,
                                   const MCFixup &Fixup,

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -36,7 +36,7 @@
 #include "llvm/Target/TargetOptions.h"
 #include <limits>
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "X86GenInstrInfo.inc"
 
 using namespace llvm;
@@ -92,6 +92,9 @@ struct X86OpTblEntry {
   uint16_t Flags;
 };
 
+// Pin the vtable to this file.
+void X86InstrInfo::anchor() {}
+
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
   : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
                      ? X86::ADJCALLSTACKDOWN64

llvm/lib/Target/X86/X86InstrInfo.h

@@ -152,6 +152,8 @@ class X86InstrInfo : public X86GenInstrInfo {
                             MemOp2RegOpTableType &M2RTable,
                             unsigned RegOp, unsigned MemOp, unsigned Flags);
 
+  virtual void anchor();
+
 public:
   explicit X86InstrInfo(X86TargetMachine &tm);
 

llvm/lib/Target/XCore/XCoreInstrInfo.cpp

@@ -22,7 +22,7 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
-#define GET_INSTRINFO_CTOR
+#define GET_INSTRINFO_CTOR_DTOR
 #include "XCoreGenInstrInfo.inc"
 
 namespace llvm {
@@ -39,6 +39,10 @@ namespace XCore {
 
 using namespace llvm;
 
+
+// Pin the vtable to this file.
+void XCoreInstrInfo::anchor() {}
+
 XCoreInstrInfo::XCoreInstrInfo()
   : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
     RI() {

llvm/lib/Target/XCore/XCoreInstrInfo.h

@@ -24,6 +24,7 @@ namespace llvm {
 
 class XCoreInstrInfo : public XCoreGenInstrInfo {
   const XCoreRegisterInfo RI;
+  virtual void anchor();
 public:
   XCoreInstrInfo();
 

llvm/tools/llvm-stress/llvm-stress.cpp

@@ -128,7 +128,7 @@ public:
     BB(Block),PT(PT),Ran(R),Context(BB->getContext()) {}
 
   /// virtual D'tor to silence warnings.
-  virtual ~Modifier() {}
+  virtual ~Modifier();
 
   /// Add a new instruction.
   virtual void Act() = 0;
@@ -287,6 +287,7 @@ protected:
 
 struct LoadModifier: public Modifier {
   LoadModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~LoadModifier();
   virtual void Act() {
     // Try to use predefined pointers. If non exist, use undef pointer value;
     Value *Ptr = getRandomPointerValue();
@@ -297,6 +298,7 @@ struct LoadModifier: public Modifier {
 
 struct StoreModifier: public Modifier {
   StoreModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~StoreModifier();
   virtual void Act() {
     // Try to use predefined pointers. If non exist, use undef pointer value;
     Value *Ptr = getRandomPointerValue();
@@ -315,6 +317,7 @@ struct StoreModifier: public Modifier {
 
 struct BinModifier: public Modifier {
   BinModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~BinModifier();
 
   virtual void Act() {
     Value *Val0 = getRandomVal();
@@ -359,6 +362,8 @@ struct BinModifier: public Modifier {
 /// Generate constant values.
 struct ConstModifier: public Modifier {
   ConstModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~ConstModifier();
+
   virtual void Act() {
     Type *Ty = pickType();
 
@@ -405,6 +410,7 @@ struct ConstModifier: public Modifier {
 
 struct AllocaModifier: public Modifier {
   AllocaModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R){}
+  virtual ~AllocaModifier();
 
   virtual void Act() {
     Type *Tp = pickType();
@@ -415,6 +421,7 @@ struct AllocaModifier: public Modifier {
 struct ExtractElementModifier: public Modifier {
   ExtractElementModifier(BasicBlock *BB, PieceTable *PT, Random *R):
     Modifier(BB, PT, R) {}
+  virtual ~ExtractElementModifier();
 
   virtual void Act() {
     Value *Val0 = getRandomVectorValue();
@@ -428,6 +435,8 @@ struct ExtractElementModifier: public Modifier {
 
 struct ShuffModifier: public Modifier {
   ShuffModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~ShuffModifier();
+
   virtual void Act() {
 
     Value *Val0 = getRandomVectorValue();
@@ -456,6 +465,7 @@ struct ShuffModifier: public Modifier {
 struct InsertElementModifier: public Modifier {
   InsertElementModifier(BasicBlock *BB, PieceTable *PT, Random *R):
     Modifier(BB, PT, R) {}
+  virtual ~InsertElementModifier();
 
   virtual void Act() {
     Value *Val0 = getRandomVectorValue();
@@ -472,6 +482,8 @@ struct InsertElementModifier: public Modifier {
 
 struct CastModifier: public Modifier {
   CastModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~CastModifier();
+
   virtual void Act() {
 
     Value *V = getRandomVal();
@@ -558,6 +570,7 @@ struct CastModifier: public Modifier {
 struct SelectModifier: public Modifier {
   SelectModifier(BasicBlock *BB, PieceTable *PT, Random *R):
     Modifier(BB, PT, R) {}
+  virtual ~SelectModifier();
 
   virtual void Act() {
     // Try a bunch of different select configuration until a valid one is found.
@@ -582,6 +595,8 @@ struct SelectModifier: public Modifier {
 
 struct CmpModifier: public Modifier {
   CmpModifier(BasicBlock *BB, PieceTable *PT, Random *R):Modifier(BB, PT, R) {}
+  virtual ~CmpModifier();
+
   virtual void Act() {
 
     Value *Val0 = getRandomVal();
@@ -607,6 +622,20 @@ struct CmpModifier: public Modifier {
   }
 };
 
+// Use out-of-line definitions to prevent weak vtables.
+Modifier::~Modifier() {}
+LoadModifier::~LoadModifier() {}
+StoreModifier::~StoreModifier() {}
+BinModifier::~BinModifier() {}
+ConstModifier::~ConstModifier() {}
+AllocaModifier::~AllocaModifier() {}
+ExtractElementModifier::~ExtractElementModifier() {}
+ShuffModifier::~ShuffModifier() {}
+InsertElementModifier::~InsertElementModifier() {}
+CastModifier::~CastModifier() {}
+SelectModifier::~SelectModifier() {}
+CmpModifier::~CmpModifier() {}
+
 void FillFunction(Function *F, Random &R) {
   // Create a legal entry block.
   BasicBlock *BB = BasicBlock::Create(F->getContext(), "BB", F);

llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp

@@ -13,9 +13,12 @@
 namespace llvm {
 
 struct VirtualRefCounted : public RefCountedBaseVPTR {
-  virtual void f() {}
+  virtual void f();
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+void VirtualRefCounted::f() {}
+
 // Run this test with valgrind to detect memory leaks.
 TEST(IntrusiveRefCntPtr, RefCountedBaseVPTRCopyDoesNotLeak) {
   VirtualRefCounted *V1 = new VirtualRefCounted;

llvm/unittests/ExecutionEngine/MCJIT/MCJITCAPITest.cpp

@@ -83,14 +83,8 @@ protected:
     UnsupportedOSs.push_back(Triple::Cygwin);
   }
   
-  virtual void SetUp() {
-    didCallAllocateCodeSection = false;
-    Module = 0;
-    Function = 0;
-    Engine = 0;
-    Error = 0;
-  }
-  
+  virtual void SetUp();
+
   virtual void TearDown() {
     if (Engine)
       LLVMDisposeExecutionEngine(Engine);
@@ -157,6 +151,15 @@ protected:
   char *Error;
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+void MCJITCAPITest::SetUp() {
+  didCallAllocateCodeSection = false;
+  Module = 0;
+  Function = 0;
+  Engine = 0;
+  Error = 0;
+}
+
 TEST_F(MCJITCAPITest, simple_function) {
   SKIP_UNSUPPORTED_PLATFORM;
   

llvm/unittests/ExecutionEngine/MCJIT/MCJITMultipleModuleTest.cpp

@@ -18,7 +18,13 @@
 
 using namespace llvm;
 
-class MCJITMultipleModuleTest : public testing::Test, public MCJITTestBase {};
+class MCJITMultipleModuleTest : public testing::Test, public MCJITTestBase {
+public:
+  virtual ~MCJITMultipleModuleTest();
+};
+
+// Provide out-of-line definition to prevent weak vtable.
+MCJITMultipleModuleTest::~MCJITMultipleModuleTest() {}
 
 namespace {
 

llvm/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp

@@ -21,11 +21,14 @@ using namespace llvm;
 class MCJITTest : public testing::Test, public MCJITTestBase {
 protected:
 
-  virtual void SetUp() {
-    M.reset(createEmptyModule("<main>"));
-  }
+  virtual void SetUp();
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+void MCJITTest::SetUp() {
+  M.reset(createEmptyModule("<main>"));
+}
+
 namespace {
 
 // FIXME: Ensure creating an execution engine does not crash when constructed

llvm/utils/TableGen/CodeGenSchedule.cpp

@@ -38,12 +38,16 @@ static void dumpIdxVec(const SmallVectorImpl<unsigned> &V) {
 
 // (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp.
 struct InstrsOp : public SetTheory::Operator {
-  void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
-             ArrayRef<SMLoc> Loc) {
-    ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc);
-  }
+  virtual void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
+                     ArrayRef<SMLoc> Loc);
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+void InstrsOp::apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
+                     ArrayRef<SMLoc> Loc) {
+  ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc);
+}
+
 // (instregex "OpcPat",...) Find all instructions matching an opcode pattern.
 //
 // TODO: Since this is a prefix match, perform a binary search over the
@@ -56,35 +60,39 @@ struct InstRegexOp : public SetTheory::Operator {
   const CodeGenTarget &Target;
   InstRegexOp(const CodeGenTarget &t): Target(t) {}
 
-  void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
-             ArrayRef<SMLoc> Loc) {
-    SmallVector<Regex*, 4> RegexList;
-    for (DagInit::const_arg_iterator
-           AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) {
-      StringInit *SI = dyn_cast<StringInit>(*AI);
-      if (!SI)
-        PrintFatalError(Loc, "instregex requires pattern string: "
-          + Expr->getAsString());
-      std::string pat = SI->getValue();
-      // Implement a python-style prefix match.
-      if (pat[0] != '^') {
-        pat.insert(0, "^(");
-        pat.insert(pat.end(), ')');
-      }
-      RegexList.push_back(new Regex(pat));
-    }
-    for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
-           E = Target.inst_end(); I != E; ++I) {
-      for (SmallVectorImpl<Regex*>::iterator
-             RI = RegexList.begin(), RE = RegexList.end(); RI != RE; ++RI) {
-        if ((*RI)->match((*I)->TheDef->getName()))
-          Elts.insert((*I)->TheDef);
-      }
-    }
-    DeleteContainerPointers(RegexList);
-  }
+  virtual void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
+                     ArrayRef<SMLoc> Loc);
 };
 
+// Provide out-of-line definition to prevent weak vtable.
+void InstRegexOp::apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
+                       ArrayRef<SMLoc> Loc) {
+  SmallVector<Regex*, 4> RegexList;
+  for (DagInit::const_arg_iterator
+       AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) {
+    StringInit *SI = dyn_cast<StringInit>(*AI);
+    if (!SI)
+      PrintFatalError(Loc, "instregex requires pattern string: "
+                      + Expr->getAsString());
+    std::string pat = SI->getValue();
+    // Implement a python-style prefix match.
+    if (pat[0] != '^') {
+      pat.insert(0, "^(");
+      pat.insert(pat.end(), ')');
+    }
+    RegexList.push_back(new Regex(pat));
+  }
+  for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
+       E = Target.inst_end(); I != E; ++I) {
+    for (SmallVectorImpl<Regex*>::iterator
+         RI = RegexList.begin(), RE = RegexList.end(); RI != RE; ++RI) {
+      if ((*RI)->match((*I)->TheDef->getName()))
+        Elts.insert((*I)->TheDef);
+    }
+  }
+  DeleteContainerPointers(RegexList);
+}
+
 /// CodeGenModels ctor interprets machine model records and populates maps.
 CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
                                        const CodeGenTarget &TGT):