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Thumb disassembler did not handle tBRIND (indirect branch) properly. 

rdar://problem/9280370

llvm-svn: 129480
This commit is contained in:
Johnny Chen 2011-04-13 21:59:01 +00:00
parent 13b5a2c2f8
commit d0fb04f437
2 changed files with 13 additions and 6 deletions
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16
llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -479,6 +479,7 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
// tBX_RET: 0 operand
// tBX_RET_vararg: Rm
// tBLXr_r9: Rm
// tBRIND: Rm
static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -486,14 +487,17 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
if (NumOps == 0)
return true;
// BX/BLX has 1 reg operand: Rm.
if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
// Handling the two predicate operands before the reg operand.
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
return false;
// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX_Rm || Opcode==ARM::tBRIND) {
if (Opcode != ARM::tBRIND) {
// Handling the two predicate operands before the reg operand.
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
return false;
NumOpsAdded += 2;
}
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
getT1Rm(insn))));
NumOpsAdded = 3;
NumOpsAdded += 1;
return true;
}

3
llvm/test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -244,3 +244,6 @@
# CHECK: mov.w r3, #4294967295
0x4f 0xf0 0xff 0x33
# CHECK: mov pc, sp
0xef 0x46