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Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure). 

Added a test.

llvm-svn: 175144
This commit is contained in:
Elena Demikhovsky 2013-02-14 08:20:26 +00:00
parent d7d8625f4c
commit d0a0cc80cd
2 changed files with 31 additions and 3 deletions
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20
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -6662,9 +6662,10 @@ X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
}
LLVMContext *Context = DAG.getContext();
unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
EVT NeVT = EVT::getIntegerVT(*Context, NBits);
EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
if (!isTypeLegal(NVT))
return SDValue();
@ -6683,8 +6684,21 @@ X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
// If it's foldable, i.e. normal load with single use, we will let code
// selection to fold it. Otherwise, we will short the conversion sequence.
if (CIdx && CIdx->getZExtValue() == 0 &&
(!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
(!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
// The "ext_vec_elt" node is wider than the result node.
// In this case we should extract subvector from V.
// (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
EVT FullVT = V.getValueType();
EVT SubVecVT = EVT::getVectorVT(*Context,
FullVT.getVectorElementType(),
FullVT.getVectorNumElements()/Ratio);
V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
DAG.getIntPtrConstant(0));
}
V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
}
}
return DAG.getNode(ISD::BITCAST, DL, VT,

14
llvm/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-pc-win32 | FileCheck %s
; CHECK: test
; CHECK: vpmovzxwd
; CHECK: vpmovzxwd
define void @test(<4 x i64> %a, <4 x i16>* %buf) {
%ex1 = extractelement <4 x i64> %a, i32 0
%ex2 = extractelement <4 x i64> %a, i32 1
%x1 = bitcast i64 %ex1 to <4 x i16>
%x2 = bitcast i64 %ex2 to <4 x i16>
%Sh = shufflevector <4 x i16> %x1, <4 x i16> %x2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
store <4 x i16> %Sh, <4 x i16>* %buf, align 1
ret void
}