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GlobalISel: Implement narrowing for G_LOAD 

llvm-svn: 292461
This commit is contained in:
Justin Bogner 2017-01-19 01:05:48 +00:00
parent 1f5c505437
commit d09c3ce6c0
2 changed files with 36 additions and 0 deletions
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26
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -161,6 +161,32 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
MI.eraseFromParent();
return Legalized;
}
case TargetOpcode::G_LOAD: {
unsigned NarrowSize = NarrowTy.getSizeInBits();
int NumParts =
MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
LLT NarrowPtrTy = LLT::pointer(
MRI.getType(MI.getOperand(1).getReg()).getAddressSpace(), NarrowSize);
SmallVector<unsigned, 2> DstRegs;
SmallVector<uint64_t, 2> Indexes;
for (int i = 0; i < NumParts; ++i) {
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
unsigned SrcReg = MRI.createGenericVirtualRegister(NarrowPtrTy);
unsigned Offset = MRI.createGenericVirtualRegister(LLT::scalar(64));
MIRBuilder.buildConstant(Offset, i * NarrowSize / 8);
MIRBuilder.buildGEP(SrcReg, MI.getOperand(1).getReg(), Offset);
MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
DstRegs.push_back(DstReg);
Indexes.push_back(i * NarrowSize);
}
unsigned DstReg = MI.getOperand(0).getReg();
MIRBuilder.buildSequence(DstReg, DstRegs, Indexes);
MI.eraseFromParent();
return Legalized;
}
case TargetOpcode::G_STORE: {
unsigned NarrowSize = NarrowTy.getSizeInBits();
int NumParts =

10
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
View File

@ -24,6 +24,7 @@ registers:
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@ -51,6 +52,15 @@ body: |
; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0
; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64)
; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD [[GEP0]](p0) :: (load 16 from %ir.addr)
; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
; CHECK: %8(s128) = G_SEQUENCE [[LOAD0]](s64), 0, [[LOAD1]](s64), 64
%8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
...
---