SchedMachineModel: compress the CPU's WriteLatencyTable.
llvm-svn: 164199
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@ -270,6 +270,21 @@ unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
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return 0;
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return 0;
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}
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}
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bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
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for (unsigned i = 0, e = SchedReads.size(); i < e; ++i) {
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Record *ReadDef = SchedReads[i].TheDef;
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if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
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continue;
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RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");
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if (std::find(ValidWrites.begin(), ValidWrites.end(), WriteDef)
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!= ValidWrites.end()) {
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return true;
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}
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}
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return false;
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}
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namespace llvm {
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namespace llvm {
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void splitSchedReadWrites(const RecVec &RWDefs,
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void splitSchedReadWrites(const RecVec &RWDefs,
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RecVec &WriteDefs, RecVec &ReadDefs) {
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RecVec &WriteDefs, RecVec &ReadDefs) {
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@ -284,6 +284,9 @@ public:
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unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
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unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
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// Return true if the given write record is referenced by a ReadAdvance.
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bool hasReadOfWrite(Record *WriteDef) const;
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// Check if any instructions are assigned to an explicit itinerary class other
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// Check if any instructions are assigned to an explicit itinerary class other
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// than NoItinerary.
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// than NoItinerary.
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bool hasItineraryClasses() const { return NumItineraryClasses > 0; }
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bool hasItineraryClasses() const { return NumItineraryClasses > 0; }
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@ -36,6 +36,7 @@ class SubtargetEmitter {
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std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
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std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
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std::vector<MCWriteProcResEntry> WriteProcResources;
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std::vector<MCWriteProcResEntry> WriteProcResources;
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std::vector<MCWriteLatencyEntry> WriteLatencies;
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std::vector<MCWriteLatencyEntry> WriteLatencies;
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std::vector<std::string> WriterNames;
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std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
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std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
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// Reserve an invalid entry at index 0
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// Reserve an invalid entry at index 0
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@ -43,6 +44,7 @@ class SubtargetEmitter {
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ProcSchedClasses.resize(1);
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ProcSchedClasses.resize(1);
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WriteProcResources.resize(1);
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WriteProcResources.resize(1);
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WriteLatencies.resize(1);
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WriteLatencies.resize(1);
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WriterNames.push_back("InvalidWrite");
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ReadAdvanceEntries.resize(1);
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ReadAdvanceEntries.resize(1);
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}
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}
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};
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};
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@ -774,6 +776,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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// Sum resources across all operand writes.
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// Sum resources across all operand writes.
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std::vector<MCWriteProcResEntry> WriteProcResources;
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std::vector<MCWriteProcResEntry> WriteProcResources;
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std::vector<MCWriteLatencyEntry> WriteLatencies;
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std::vector<MCWriteLatencyEntry> WriteLatencies;
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std::vector<std::string> WriterNames;
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std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
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std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
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for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
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for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
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IdxVec WriteSeq;
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IdxVec WriteSeq;
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@ -782,7 +785,14 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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// For each operand, create a latency entry.
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// For each operand, create a latency entry.
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MCWriteLatencyEntry WLEntry;
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MCWriteLatencyEntry WLEntry;
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WLEntry.Cycles = 0;
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WLEntry.Cycles = 0;
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WLEntry.WriteResourceID = WriteSeq.back();
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unsigned WriteID = WriteSeq.back();
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WriterNames.push_back(SchedModels.getSchedWrite(WriteID).Name);
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// If this Write is not referenced by a ReadAdvance, don't distinguish it
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// from other WriteLatency entries.
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if (!SchedModels.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef)) {
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WriteID = 0;
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}
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WLEntry.WriteResourceID = WriteID;
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for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
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for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
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WSI != WSE; ++WSI) {
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WSI != WSE; ++WSI) {
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@ -881,12 +891,22 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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std::search(SchedTables.WriteLatencies.begin(),
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std::search(SchedTables.WriteLatencies.begin(),
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SchedTables.WriteLatencies.end(),
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SchedTables.WriteLatencies.end(),
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WriteLatencies.begin(), WriteLatencies.end());
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WriteLatencies.begin(), WriteLatencies.end());
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if (WLPos != SchedTables.WriteLatencies.end())
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if (WLPos != SchedTables.WriteLatencies.end()) {
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SCDesc.WriteLatencyIdx = WLPos - SchedTables.WriteLatencies.begin();
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unsigned idx = WLPos - SchedTables.WriteLatencies.begin();
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SCDesc.WriteLatencyIdx = idx;
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for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i)
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if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) ==
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std::string::npos) {
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SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i];
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}
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}
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else {
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else {
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SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
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SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
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SchedTables.WriteLatencies.insert(WLPos, WriteLatencies.begin(),
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SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
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WriteLatencies.begin(),
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WriteLatencies.end());
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WriteLatencies.end());
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SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
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WriterNames.begin(), WriterNames.end());
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}
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}
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// ReadAdvanceEntries must remain in operand order.
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// ReadAdvanceEntries must remain in operand order.
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SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
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SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
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@ -935,8 +955,7 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
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<< format("%2d", WLEntry.WriteResourceID) << "}";
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<< format("%2d", WLEntry.WriteResourceID) << "}";
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if (WLIdx + 1 < WLEnd)
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if (WLIdx + 1 < WLEnd)
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OS << ',';
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OS << ',';
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OS << " // #" << WLIdx << " "
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OS << " // #" << WLIdx << " " << SchedTables.WriterNames[WLIdx] << '\n';
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<< SchedModels.getSchedWrite(WLEntry.WriteResourceID).Name << '\n';
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}
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}
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OS << "}; // " << Target << "WriteLatencyTable\n";
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OS << "}; // " << Target << "WriteLatencyTable\n";
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