[ARM] Add MVE vector shift instructions.

This includes saturating and non-saturating shifts, both with immediate shift count and with the shift counts given by another vector register; VSHLC (in which the bits shifted out of each active vector lane are shifted in to the next active lane); and also VMOVL, which is enough like an immediate shift that it didn't fit too badly in this category. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62672 llvm-svn: 363696
2019-06-18 16:19:59 +00:00 · 2019-06-18 16:19:59 +00:00 · cfc70782d7
parent faaf1a5366
commit cfc70782d7
6 changed files with 1816 additions and 4 deletions
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@ -779,6 +779,32 @@ def imm1_16 : Operand<i32>, ImmLeaf<i32, [{
  let ParserMatchClass = Imm1_16AsmOperand;
 }

+def MVEShiftImm1_7AsmOperand: ImmAsmOperand<1,7> {
+  let Name = "MVEShiftImm1_7";
+  // Reason we're doing this is because instruction vshll.s8 t1 encoding
+  // accepts 1,7 but the t2 encoding accepts 8.  By doing this we can get a
+  // better diagnostic message if someone uses bigger immediate than the t1/t2
+  // encodings allow.
+  let DiagnosticString = "operand must be an immediate in the range [1,8]";
+}
+def mve_shift_imm1_7 : Operand<i32> {
+  let ParserMatchClass = MVEShiftImm1_7AsmOperand;
+  let EncoderMethod = "getMVEShiftImmOpValue";
+}
+
+def MVEShiftImm1_15AsmOperand: ImmAsmOperand<1,15> {
+  let Name = "MVEShiftImm1_15";
+  // Reason we're doing this is because instruction vshll.s16 t1 encoding
+  // accepts 1,15 but the t2 encoding accepts 16.  By doing this we can get a
+  // better diagnostic message if someone uses bigger immediate than the t1/t2
+  // encodings allow.
+  let DiagnosticString = "operand must be an immediate in the range [1,16]";
+}
+def mve_shift_imm1_15 : Operand<i32> {
+  let ParserMatchClass = MVEShiftImm1_15AsmOperand;
+  let EncoderMethod = "getMVEShiftImmOpValue";
+}
+
 // Define ARM specific addressing modes.
 // addrmode_imm12 := reg +/- imm12
 //
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@ -670,6 +670,553 @@ defm MVE_VMIN : MVE_VMINMAX_all_sizes<"vmin", 0b1>;

 // end of mve_comp instructions

+// start of mve_imm_shift instructions
+
+def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
+                      (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
+                      NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
+                      vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {
+  bits<5> imm;
+  bits<4> Qd;
+  bits<4> RdmDest;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b101;
+  let Inst{22} = Qd{3};
+  let Inst{21} = 0b1;
+  let Inst{20-16} = imm{4-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-4} = 0b011111100;
+  let Inst{3-0} = RdmDest{3-0};
+}
+
+class MVE_shift_imm<dag oops, dag iops, string iname, string suffix,
+                    string ops, vpred_ops vpred, string cstr,
+                    list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U,
+              list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
+                  iname, suffix, "$Qd, $Qm", vpred_r, "",
+                  pattern> {
+  let Inst{28} = U;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b1;
+  let Inst{20-19} = sz{1-0};
+  let Inst{18-16} = 0b000;
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+multiclass MVE_VMOVL_shift_half<string iname, string suffix, bits<2> sz, bit U,
+                                list<dag> pattern=[]> {
+  def bh : MVE_VMOVL<!strconcat(iname, "b"), suffix, sz, U, pattern> {
+    let Inst{12} = 0b0;
+  }
+  def th : MVE_VMOVL<!strconcat(iname, "t"), suffix, sz, U, pattern> {
+    let Inst{12} = 0b1;
+  }
+}
+
+defm MVE_VMOVLs8 : MVE_VMOVL_shift_half<"vmovl", "s8", 0b01, 0b0>;
+defm MVE_VMOVLu8 : MVE_VMOVL_shift_half<"vmovl", "u8", 0b01, 0b1>;
+defm MVE_VMOVLs16 : MVE_VMOVL_shift_half<"vmovl", "s16", 0b10, 0b0>;
+defm MVE_VMOVLu16 : MVE_VMOVL_shift_half<"vmovl", "u16", 0b10, 0b1>;
+
+class MVE_VSHLL_imm<string iname, string suffix, bit U, bit th,
+                    dag immops, list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_r, "", pattern> {
+  let Inst{28} = U;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b1;
+  let Inst{12} = th;
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+// The immediate VSHLL instructions accept shift counts from 1 up to
+// the lane width (8 or 16), but the full-width shifts have an
+// entirely separate encoding, given below with 'lw' in the name.
+
+class MVE_VSHLL_imm8<string iname, string suffix,
+                     bit U, bit th, list<dag> pattern=[]>
+  : MVE_VSHLL_imm<iname, suffix, U, th, (ins mve_shift_imm1_7:$imm), pattern> {
+  bits<3> imm;
+  let Inst{20-19} = 0b01;
+  let Inst{18-16} = imm;
+}
+
+class MVE_VSHLL_imm16<string iname, string suffix,
+                      bit U, bit th, list<dag> pattern=[]>
+  : MVE_VSHLL_imm<iname, suffix, U, th, (ins mve_shift_imm1_15:$imm), pattern> {
+  bits<4> imm;
+  let Inst{20} = 0b1;
+  let Inst{19-16} = imm;
+}
+
+def MVE_VSHLL_imms8bh  : MVE_VSHLL_imm8 <"vshllb", "s8", 0b0, 0b0>;
+def MVE_VSHLL_imms8th  : MVE_VSHLL_imm8 <"vshllt", "s8", 0b0, 0b1>;
+def MVE_VSHLL_immu8bh  : MVE_VSHLL_imm8 <"vshllb", "u8", 0b1, 0b0>;
+def MVE_VSHLL_immu8th  : MVE_VSHLL_imm8 <"vshllt", "u8", 0b1, 0b1>;
+def MVE_VSHLL_imms16bh : MVE_VSHLL_imm16<"vshllb", "s16", 0b0, 0b0>;
+def MVE_VSHLL_imms16th : MVE_VSHLL_imm16<"vshllt", "s16", 0b0, 0b1>;
+def MVE_VSHLL_immu16bh : MVE_VSHLL_imm16<"vshllb", "u16", 0b1, 0b0>;
+def MVE_VSHLL_immu16th : MVE_VSHLL_imm16<"vshllt", "u16", 0b1, 0b1>;
+
+class MVE_VSHLL_by_lane_width<string iname, string suffix, bits<2> size,
+                              bit U, string ops, list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
+                  iname, suffix, ops, vpred_r, "", pattern> {
+  let Inst{28} = U;
+  let Inst{25-23} = 0b100;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size{1-0};
+  let Inst{17-16} = 0b01;
+  let Inst{11-6} = 0b111000;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+multiclass MVE_VSHLL_lw<string iname, string suffix, bits<2> sz, bit U,
+                              string ops, list<dag> pattern=[]> {
+  def bh : MVE_VSHLL_by_lane_width<iname#"b", suffix, sz, U, ops, pattern> {
+    let Inst{12} = 0b0;
+  }
+  def th : MVE_VSHLL_by_lane_width<iname#"t", suffix, sz, U, ops, pattern> {
+    let Inst{12} = 0b1;
+  }
+}
+
+defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
+defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
+defm MVE_VSHLL_lwu8  : MVE_VSHLL_lw<"vshll", "u8",  0b00, 0b1, "$Qd, $Qm, #8">;
+defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
+
+class MVE_VxSHRN<string iname, string suffix, bit bit_12, bit bit_28,
+               dag immops, list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b1;
+}
+
+def MVE_VRSHRNi16bh : MVE_VxSHRN<
+    "vrshrnb", "i16", 0b0, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VRSHRNi16th : MVE_VxSHRN<
+    "vrshrnt", "i16", 0b1, 0b1,(ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VRSHRNi32bh : MVE_VxSHRN<
+    "vrshrnb", "i32", 0b0, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def MVE_VRSHRNi32th : MVE_VxSHRN<
+    "vrshrnt", "i32", 0b1, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+def MVE_VSHRNi16bh : MVE_VxSHRN<
+    "vshrnb", "i16", 0b0, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VSHRNi16th : MVE_VxSHRN<
+    "vshrnt", "i16", 0b1, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VSHRNi32bh : MVE_VxSHRN<
+    "vshrnb", "i32", 0b0, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def MVE_VSHRNi32th : MVE_VxSHRN<
+    "vshrnt", "i32", 0b1, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+class MVE_VxQRSHRUN<string iname, string suffix, bit bit_28, bit bit_12, dag immops,
+                 list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{28} = bit_28;
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def MVE_VQRSHRUNs16bh : MVE_VxQRSHRUN<
+    "vqrshrunb", "s16", 0b1, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VQRSHRUNs16th : MVE_VxQRSHRUN<
+    "vqrshrunt", "s16", 0b1, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VQRSHRUNs32bh : MVE_VxQRSHRUN<
+    "vqrshrunb", "s32", 0b1, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def MVE_VQRSHRUNs32th : MVE_VxQRSHRUN<
+    "vqrshrunt", "s32", 0b1, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+def MVE_VQSHRUNs16bh : MVE_VxQRSHRUN<
+    "vqshrunb", "s16", 0b0, 0b0, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VQSHRUNs16th : MVE_VxQRSHRUN<
+    "vqshrunt", "s16", 0b0, 0b1, (ins shr_imm8:$imm)> {
+  let Inst{20-19} = 0b01;
+}
+def MVE_VQSHRUNs32bh : MVE_VxQRSHRUN<
+    "vqshrunb", "s32", 0b0, 0b0, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+def MVE_VQSHRUNs32th : MVE_VxQRSHRUN<
+    "vqshrunt", "s32", 0b0, 0b1, (ins shr_imm16:$imm)> {
+  let Inst{20} = 0b1;
+}
+
+class MVE_VxQRSHRN<string iname, string suffix, bit bit_0, bit bit_12,
+                   dag immops, list<dag> pattern=[]>
+  : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
+                  iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
+                  pattern> {
+  bits<5> imm;
+
+  let Inst{25-23} = 0b101;
+  let Inst{21} = 0b0;
+  let Inst{20-16} = imm{4-0};
+  let Inst{12} = bit_12;
+  let Inst{11-6} = 0b111101;
+  let Inst{4} = 0b0;
+  let Inst{0} = bit_0;
+}
+
+multiclass MVE_VxQRSHRN_types<string iname, bit bit_0, bit bit_12> {
+  def s16 : MVE_VxQRSHRN<iname, "s16", bit_0, bit_12, (ins shr_imm8:$imm)> {
+    let Inst{28} = 0b0;
+    let Inst{20-19} = 0b01;
+  }
+  def u16 : MVE_VxQRSHRN<iname, "u16", bit_0, bit_12, (ins shr_imm8:$imm)> {
+    let Inst{28} = 0b1;
+    let Inst{20-19} = 0b01;
+  }
+  def s32 : MVE_VxQRSHRN<iname, "s32", bit_0, bit_12, (ins shr_imm16:$imm)> {
+    let Inst{28} = 0b0;
+    let Inst{20} = 0b1;
+  }
+  def u32 : MVE_VxQRSHRN<iname, "u32", bit_0, bit_12, (ins shr_imm16:$imm)> {
+    let Inst{28} = 0b1;
+    let Inst{20} = 0b1;
+  }
+}
+
+defm MVE_VQRSHRNbh : MVE_VxQRSHRN_types<"vqrshrnb", 0b1, 0b0>;
+defm MVE_VQRSHRNth : MVE_VxQRSHRN_types<"vqrshrnt", 0b1, 0b1>;
+defm MVE_VQSHRNbh  : MVE_VxQRSHRN_types<"vqshrnb", 0b0, 0b0>;
+defm MVE_VQSHRNth  : MVE_VxQRSHRN_types<"vqshrnt", 0b0, 0b1>;
+
+// end of mve_imm_shift instructions
+
+// start of mve_shift instructions
+
+class MVE_shift_by_vec<string iname, string suffix, bit U,
+                       bits<2> size, bit bit_4, bit bit_8>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm, MQPR:$Qn), NoItinerary,
+           iname, suffix, "$Qd, $Qm, $Qn", vpred_r, "", []> {
+  // Shift instructions which take a vector of shift counts
+  bits<4> Qd;
+  bits<4> Qm;
+  bits<4> Qn;
+
+  let Inst{28} = U;
+  let Inst{25-24} = 0b11;
+  let Inst{23} = 0b0;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0010;
+  let Inst{8} = bit_8;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{4} = bit_4;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> {
+  def s8  : MVE_shift_by_vec<iname, "s8", 0b0, 0b00, bit_4, bit_8>;
+  def s16 : MVE_shift_by_vec<iname, "s16", 0b0, 0b01, bit_4, bit_8>;
+  def s32 : MVE_shift_by_vec<iname, "s32", 0b0, 0b10, bit_4, bit_8>;
+  def u8  : MVE_shift_by_vec<iname, "u8", 0b1, 0b00, bit_4, bit_8>;
+  def u16 : MVE_shift_by_vec<iname, "u16", 0b1, 0b01, bit_4, bit_8>;
+  def u32 : MVE_shift_by_vec<iname, "u32", 0b1, 0b10, bit_4, bit_8>;
+}
+
+defm MVE_VSHL_by_vec   : mve_shift_by_vec_multi<"vshl",   0b0, 0b0>;
+defm MVE_VQSHL_by_vec  : mve_shift_by_vec_multi<"vqshl",  0b1, 0b0>;
+defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
+defm MVE_VRSHL_by_vec  : mve_shift_by_vec_multi<"vrshl",  0b0, 0b1>;
+
+class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
+                         string ops, vpred_ops vpred, string cstr,
+                         list<dag> pattern=[]>
+  : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{23} = 0b1;
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-11} = 0b00;
+  let Inst{7-6} = 0b01;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b1;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b0;
+}
+
+class MVE_VSxI_imm<string iname, string suffix, bit bit_8, dag imm>
+  : MVE_shift_with_imm<iname, suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qd_src, MQPR:$Qm), imm),
+                       "$Qd, $Qm, $imm", vpred_n, "$Qd = $Qd_src"> {
+  bits<6> imm;
+  let Inst{28} = 0b1;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-9} = 0b10;
+  let Inst{8} = bit_8;
+}
+
+def MVE_VSRIimm8 : MVE_VSxI_imm<"vsri", "8", 0b0, (ins shr_imm8:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSRIimm16 : MVE_VSxI_imm<"vsri", "16", 0b0, (ins shr_imm16:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSRIimm32 : MVE_VSxI_imm<"vsri", "32", 0b0, (ins shr_imm32:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+def MVE_VSLIimm8 : MVE_VSxI_imm<"vsli", "8", 0b1, (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSLIimm16 : MVE_VSxI_imm<"vsli", "16", 0b1, (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSLIimm32 : MVE_VSxI_imm<"vsli", "32", 0b1,(ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+class MVE_VQSHL_imm<string suffix, dag imm>
+  : MVE_shift_with_imm<"vqshl", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b111;
+}
+
+def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class MVE_VQSHLU_imm<string suffix, dag imm>
+  : MVE_shift_with_imm<"vqshlu", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{28} = 0b1;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b110;
+}
+
+def MVE_VQSHLU_imms8 : MVE_VQSHLU_imm<"s8", (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VQSHLU_imms16 : MVE_VQSHLU_imm<"s16", (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VQSHLU_imms32 : MVE_VQSHLU_imm<"s32", (ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+
+class MVE_VRSHR_imm<string suffix, dag imm>
+  : MVE_shift_with_imm<"vrshr", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b010;
+}
+
+def MVE_VRSHR_imms8 : MVE_VRSHR_imm<"s8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VRSHR_immu8 : MVE_VRSHR_imm<"u8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VRSHR_imms16 : MVE_VRSHR_imm<"s16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VRSHR_immu16 : MVE_VRSHR_imm<"u16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VRSHR_imms32 : MVE_VRSHR_imm<"s32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def MVE_VRSHR_immu32 : MVE_VRSHR_imm<"u32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class MVE_VSHR_imm<string suffix, dag imm>
+  : MVE_shift_with_imm<"vshr", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b000;
+}
+
+def MVE_VSHR_imms8 : MVE_VSHR_imm<"s8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSHR_immu8 : MVE_VSHR_imm<"u8", (ins shr_imm8:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSHR_imms16 : MVE_VSHR_imm<"s16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSHR_immu16 : MVE_VSHR_imm<"u16", (ins shr_imm16:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSHR_imms32 : MVE_VSHR_imm<"s32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b0;
+  let Inst{21} = 0b1;
+}
+
+def MVE_VSHR_immu32 : MVE_VSHR_imm<"u32", (ins shr_imm32:$imm)> {
+  let Inst{28} = 0b1;
+  let Inst{21} = 0b1;
+}
+
+class MVE_VSHL_imm<string suffix, dag imm>
+  : MVE_shift_with_imm<"vshl", suffix, (outs MQPR:$Qd),
+                       !con((ins MQPR:$Qm), imm), "$Qd, $Qm, $imm",
+                       vpred_r, ""> {
+  bits<6> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-24} = 0b11;
+  let Inst{21-16} = imm;
+  let Inst{10-8} = 0b101;
+}
+
+def MVE_VSHL_immi8 : MVE_VSHL_imm<"i8", (ins imm0_7:$imm)> {
+  let Inst{21-19} = 0b001;
+}
+
+def MVE_VSHL_immi16 : MVE_VSHL_imm<"i16", (ins imm0_15:$imm)> {
+  let Inst{21-20} = 0b01;
+}
+
+def MVE_VSHL_immi32 : MVE_VSHL_imm<"i32", (ins imm0_31:$imm)> {
+  let Inst{21} = 0b1;
+}
+// end of mve_shift instructions
+
 class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
  : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
  bits<3> fc;
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@ -5934,7 +5934,9 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
      Mnemonic != "sbcs" && Mnemonic != "rscs" &&
-      !(hasMVE() && Mnemonic == "vmine")) {
+      !(hasMVE() &&
+        (Mnemonic == "vmine" ||
+         Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt"))) {
    unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
    if (CC != ~0U) {
      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
@ -5975,7 +5977,10 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
    }
  }

-  if (isMnemonicVPTPredicable(Mnemonic, ExtraToken)) {
+  if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
+      Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
+      Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
+      Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt") {
    unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
    if (CC != ~0U) {
      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
@ -6509,7 +6514,13 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
  }

  // Add the VPT predication code operand, if necessary.
-  if (CanAcceptVPTPredicationCode) {
+  // FIXME: We don't add them for the instructions filtered below as these can
+  // have custom operands which need special parsing.  This parsing requires
+  // the operand to be in the same place in the OperandVector as their
+  // definition in tblgen.  Since these instructions may also have the
+  // scalar predication operand we do not add the vector one and leave until
+  // now to fix it up.
+  if (CanAcceptVPTPredicationCode && Mnemonic != "vmov") {
    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
                                      CarrySetting);
    Operands.push_back(ARMOperand::CreateVPTPred(
@ -6593,7 +6604,21 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,


  if (hasMVE()) {
-    if (CanAcceptVPTPredicationCode) {
+    if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
+        Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
+      // Very nasty hack to deal with the vector predicated variant of vmovlt
+      // the scalar predicated vmov with condition 'lt'.  We can not tell them
+      // apart until we have parsed their operands.
+      Operands.erase(Operands.begin() + 1);
+      Operands.erase(Operands.begin());
+      SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
+      SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
+                                         Mnemonic.size() - 1 + CarrySetting);
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
+      Operands.insert(Operands.begin(),
+                      ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
+    } else if (CanAcceptVPTPredicationCode) {
      // For all other instructions, make sure only one of the two
      // predication operands is left behind, depending on whether we should
      // use the vector predication.
@ -11244,6 +11269,18 @@ unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
        if (CE->getValue() == 0)
          return Match_Success;
    break;
+  case MCK__35_8:
+    if (Op.isImm())
+      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
+        if (CE->getValue() == 8)
+          return Match_Success;
+    break;
+  case MCK__35_16:
+    if (Op.isImm())
+      if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
+        if (CE->getValue() == 16)
+          return Match_Success;
+    break;
  case MCK_ModImm:
    if (Op.isImm()) {
      const MCExpr *SOExpr = Op.getImm();
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@ -166,6 +166,12 @@ public:
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const;

+  /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
+  /// operand.
+  uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
+
  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
  /// operand.
  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
@ -903,6 +909,41 @@ getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
  return (Rm << 3) | Rn;
 }

+/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
+/// operand.
+uint32_t
+ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
+                                        SmallVectorImpl<MCFixup> &Fixups,
+                                        const MCSubtargetInfo &STI) const {
+  // {4-0} = szimm5
+  // The value we are trying to encode is an immediate between either the
+  // range of [1-7] or [1-15] depending on whether we are dealing with the
+  // u8/s8 or the u16/s16 variants respectively.
+  // This value is encoded as follows, if ShiftImm is the value within those
+  // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
+  // or 16.
+
+  unsigned Size, ShiftImm;
+  switch(MI.getOpcode()) {
+    case ARM::MVE_VSHLL_imms16bh:
+    case ARM::MVE_VSHLL_imms16th:
+    case ARM::MVE_VSHLL_immu16bh:
+    case ARM::MVE_VSHLL_immu16th:
+      Size = 16;
+      break;
+    case ARM::MVE_VSHLL_imms8bh:
+    case ARM::MVE_VSHLL_imms8th:
+    case ARM::MVE_VSHLL_immu8bh:
+    case ARM::MVE_VSHLL_immu8th:
+      Size = 8;
+      break;
+    default:
+      llvm_unreachable("Use of operand not supported by this instruction");
+  }
+  ShiftImm = MI.getOperand(OpIdx).getImm();
+  return Size + ShiftImm;
+}
+
 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
 uint32_t ARMMCCodeEmitter::
 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
--- a/llvm/test/MC/ARM/mve-shifts.s
+++ b/llvm/test/MC/ARM/mve-shifts.s
@ -0,0 +1,576 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+# CHECK-NOFP: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+vshlc   q0, lr, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshlc   q0, lr, #33
+
+# CHECK: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+# CHECK-NOFP: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+vmovlb.s8 q0, q6
+
+# CHECK: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOFP: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+vmovlt.s8 q0, q4
+
+# CHECK: vpt.i8 eq, q0, q0
+# CHECK-NOFP: vpt.i8 eq, q0, q0
+# CHECK: vmovltt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOFP: vmovltt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+vpt.i8 eq, q0, q0
+vmovltt.s8 q0, q4
+
+# CHECK: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+# CHECK-NOFP: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+vmovlb.u8 q0, q0
+
+# CHECK: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+# CHECK-NOFP: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+vmovlt.u8 q0, q2
+
+# CHECK: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+# CHECK-NOFP: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+vmovlb.u16 q1, q0
+
+# CHECK: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+# CHECK-NOFP: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+vmovlt.u16 q0, q2
+
+# CHECK: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+# CHECK-NOFP: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+vshllb.s8 q0, q2, #8
+
+# CHECK: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+# CHECK-NOFP: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+vshllt.s8 q1, q5, #8
+
+# CHECK: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+# CHECK-NOFP: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+vshllb.s8 q0, q0, #7
+
+# CHECK: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+# CHECK-NOFP: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+vshllb.u8 q1, q1, #8
+
+# CHECK: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+# CHECK-NOFP: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+vshllt.u8 q0, q0, #8
+
+# CHECK: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+# CHECK-NOFP: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+vshllb.u8 q0, q0, #3
+
+# CHECK: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+# CHECK-NOFP: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+vshllb.u16 q0, q5, #16
+
+# CHECK: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+# CHECK-NOFP: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+vshllt.u16 q0, q3, #16
+
+# CHECK: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+# CHECK-NOFP: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+vshllt.s16 q0, q0, #16
+
+# CHECK: vshllt.s16 q0, q0, #14  @ encoding: [0xbe,0xee,0x40,0x1f]
+vshllt.s16 q0, q0, #14
+
+# CHECK: vshllt.s16 q0, q0, #11  @ encoding: [0xbb,0xee,0x40,0x1f]
+vshllt.s16 q0, q0, #11
+
+# CHECK: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+# CHECK-NOFP: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+vshllb.u16 q0, q2, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.s8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.u8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshllb.u8 q0, q2, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.s16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.u16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshllb.u16 q0, q2, #0
+
+# CHECK: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+# CHECK-NOFP: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+vrshrnb.i16 q0, q3, #1
+
+# CHECK: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+# CHECK-NOFP: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+vrshrnt.i16 q0, q2, #5
+
+# CHECK: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+# CHECK-NOFP: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+vrshrnb.i32 q0, q4, #8
+
+# CHECK: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+# CHECK-NOFP: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+vrshrnt.i32 q0, q2, #7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshrnb.i16 q0, q3, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshrnb.i32 q0, q3, #17
+
+# CHECK: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+# CHECK-NOFP: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+vshrnb.i16 q1, q2, #1
+
+# CHECK: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+# CHECK-NOFP: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+vshrnt.i16 q0, q1, #1
+
+# CHECK: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+# CHECK-NOFP: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+vshrnb.i32 q0, q0, #12
+
+# CHECK: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+# CHECK-NOFP: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+vshrnt.i32 q0, q2, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshrnb.i16 q1, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshrnb.i32 q1, q2, #17
+
+# CHECK: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+# CHECK-NOFP: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+vqrshrunb.s16 q0, q2, #8
+
+# CHECK: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+# CHECK-NOFP: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+vqrshrunt.s16 q0, q0, #6
+
+# CHECK: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+# CHECK-NOFP: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+vqrshrunt.s32 q0, q1, #8
+
+# CHECK: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+# CHECK-NOFP: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+vqrshrunb.s32 q0, q7, #13
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqrshrunb.s16 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqrshrunb.s32 q0, q2, #17
+
+# CHECK: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+# CHECK-NOFP: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+vqshrunb.s16 q0, q7, #5
+
+# CHECK: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+# CHECK-NOFP: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+vqshrunt.s16 q0, q1, #7
+
+# CHECK: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+# CHECK-NOFP: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+vqshrunb.s32 q0, q6, #4
+
+# CHECK: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+# CHECK-NOFP: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+vqshrunt.s32 q0, q2, #10
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqshrunt.s16 q0, q1, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqshrunb.s32 q0, q6, #17
+
+# CHECK: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+# CHECK-NOFP: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+vqrshrnb.s16 q0, q7, #8
+
+# CHECK: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+# CHECK-NOFP: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+vqrshrnt.u16 q1, q3, #4
+
+# CHECK: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+# CHECK-NOFP: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+vqrshrnb.u32 q0, q1, #7
+
+# CHECK: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+# CHECK-NOFP: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+vqrshrnt.s32 q0, q1, #11
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqrshrnb.s16 q0, q7, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqrshrnb.s32 q0, q7, #17
+
+# CHECK: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+# CHECK-NOFP: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+vqshrnb.s16 q0, q6, #5
+
+# CHECK: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+# CHECK-NOFP: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+vqshrnt.s16 q0, q1, #4
+
+# CHECK: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+# CHECK-NOFP: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+vqshrnb.u16 q0, q3, #7
+
+# CHECK: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+# CHECK-NOFP: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+vqshrnt.u16 q0, q2, #8
+
+# CHECK: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+# CHECK-NOFP: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+vqshrnt.s32 q1, q4, #3
+
+# CHECK: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+# CHECK-NOFP: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+vqshrnb.u32 q0, q2, #14
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vqshrnb.s16 q0, q6, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vqshrnb.u32 q0, q6, #17
+
+# CHECK: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+# CHECK-NOFP: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+vshl.s8 q6, q6, q6
+
+# CHECK: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+# CHECK-NOFP: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+vshl.s16 q0, q4, q2
+
+# CHECK: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+# CHECK-NOFP: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+vshl.s32 q1, q1, q5
+
+# CHECK: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+# CHECK-NOFP: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+vshl.u8 q1, q7, q2
+
+# CHECK: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+# CHECK-NOFP: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+vshl.u16 q0, q4, q0
+
+# CHECK: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+# CHECK-NOFP: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+vshl.u32 q2, q2, q4
+
+# CHECK: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+# CHECK-NOFP: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+vqshl.s8 q0, q1, q6
+
+# CHECK: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+# CHECK-NOFP: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+vqshl.s16 q4, q3, q7
+
+# CHECK: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+# CHECK-NOFP: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+vqshl.s32 q0, q5, q5
+
+# CHECK: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+# CHECK-NOFP: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+vqshl.u8 q0, q0, q6
+
+# CHECK: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+# CHECK-NOFP: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+vqshl.u16 q0, q5, q4
+
+# CHECK: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+# CHECK-NOFP: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+vqshl.u32 q1, q0, q4
+
+# CHECK: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+# CHECK-NOFP: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+vqrshl.s8 q1, q6, q1
+
+# CHECK: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+# CHECK-NOFP: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+vqrshl.s16 q2, q4, q6
+
+# CHECK: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+# CHECK-NOFP: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+vqrshl.s32 q0, q0, q5
+
+# CHECK: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+# CHECK-NOFP: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+vqrshl.u8 q0, q2, q1
+
+# CHECK: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+# CHECK-NOFP: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+vqrshl.u16 q1, q6, q0
+
+# CHECK: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+# CHECK-NOFP: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+vqrshl.u32 q0, q0, q0
+
+# CHECK: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+# CHECK-NOFP: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+vrshl.s8 q0, q6, q4
+
+# CHECK: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+# CHECK-NOFP: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+vrshl.s16 q1, q4, q7
+
+# CHECK: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+# CHECK-NOFP: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+vrshl.s32 q1, q4, q4
+
+# CHECK: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+# CHECK-NOFP: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+vrshl.u8 q0, q3, q5
+
+# CHECK: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+# CHECK-NOFP: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+vrshl.u16 q5, q6, q5
+
+# CHECK: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+# CHECK-NOFP: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+vrshl.u32 q1, q7, q3
+
+# CHECK: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+# CHECK-NOFP: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+vsri.8 q0, q2, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vsri.8 q0, q2, #9
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vsri.8 q0, q2, #0
+
+# CHECK: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+# CHECK-NOFP: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+vsri.16 q0, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vsri.16 q0, q2, #17
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vsri.16 q0, q2, #0
+
+# CHECK: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+# CHECK-NOFP: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+vsri.32 q0, q1, #15
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vsri.32 q0, q2, #33
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vsri.32 q0, q2, #0
+
+# CHECK: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+# CHECK-NOFP: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+vsli.8 q0, q3, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vsli.8 q0, q3, #8
+
+# CHECK: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+# CHECK-NOFP: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+vsli.16 q0, q1, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vsli.16 q0, q3, #16
+
+# CHECK: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+# CHECK-NOFP: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+vsli.32 q0, q1, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vsli.32 q0, q1, #32
+
+# CHECK: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+# CHECK-NOFP: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+vqshl.s8 q0, q4, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshl.s8 q0, q4, #8
+
+# CHECK: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+# CHECK-NOFP: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+vqshl.u8 q0, q6, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshl.u8 q0, q4, #8
+
+# CHECK: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+# CHECK-NOFP: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+vqshl.s16 q1, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshl.s16 q1, q2, #16
+
+# CHECK: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+# CHECK-NOFP: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+vqshl.u16 q0, q5, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshl.u16 q1, q2, #16
+
+# CHECK: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+# CHECK-NOFP: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+vqshl.s32 q1, q3, #29
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshl.s32 q1, q3, #32
+
+# CHECK: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+# CHECK-NOFP: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+vqshl.u32 q0, q2, #19
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshl.u32 q0, q2, #32
+
+# CHECK: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+# CHECK-NOFP: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+vqshlu.s8 q0, q1, #0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vqshlu.s8 q0, q1, #8
+
+# CHECK: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+# CHECK-NOFP: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+vqshlu.s16 q2, q1, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vqshlu.s16 q0, q1, #16
+
+# CHECK: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+# CHECK-NOFP: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+vqshlu.s32 q0, q4, #26
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vqshlu.s32 q0, q1, #32
+
+# CHECK: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+# CHECK-NOFP: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+vrshr.s8 q1, q3, #7
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshr.s8 q1, q3, #9
+
+# CHECK: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+# CHECK-NOFP: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+vrshr.u8 q1, q3, #2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vrshr.u8 q1, q3, #9
+
+# CHECK: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+# CHECK-NOFP: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+vrshr.s16 q0, q1, #10
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshr.s16 q0, q1, #17
+
+# CHECK: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+# CHECK-NOFP: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+vrshr.u16 q0, q5, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vrshr.u16 q0, q5, #20
+
+# CHECK: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+# CHECK-NOFP: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+vrshr.s32 q0, q5, #23
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vrshr.s32 q0, q5, #33
+
+# CHECK: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+# CHECK-NOFP: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+vrshr.u32 q0, q1, #30
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vrshr.u32 q0, q1, #55
+
+# CHECK: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+# CHECK-NOFP: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+vshr.s8 q0, q7, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshr.s8 q0, q7, #9
+
+# CHECK: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+# CHECK-NOFP: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+vshr.u8 q0, q2, #5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,8]
+vshr.u8 q0, q2, #9
+
+# CHECK: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+# CHECK-NOFP: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+vshr.s16 q0, q3, #16
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshr.s16 q0, q2, #17
+
+# CHECK: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+# CHECK-NOFP: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+vshr.u16 q7, q6, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,16]
+vshr.u16 q7, q6, #20
+
+# CHECK: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+# CHECK-NOFP: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+vshr.s32 q0, q6, #24
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshr.s32 q0, q6, #33
+
+# CHECK: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+# CHECK-NOFP: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+vshr.u32 q2, q5, #30
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
+vshr.u32 q2, q5, #33
+
+# CHECK: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+# CHECK-NOFP: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+vshl.i8 q0, q6, #6
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,7]
+vshl.i8 q0, q6, #8
+
+# CHECK: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+# CHECK-NOFP: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+vshl.i16 q1, q0, #12
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,15]
+vshl.i16 q1, q0, #16
+
+# CHECK: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+# CHECK-NOFP: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+vshl.i32 q2, q2, #26
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [0,31]
+vshl.i32 q2, q2, #33
+
+vshllt.s8 q0, q1, #1
+# CHECK: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
+# CHECK-NOFP: vshllt.s8 q0, q1, #1 @ encoding: [0xa9,0xee,0x42,0x1f]
+
+vpste
+vshlltt.s16 q0, q1, #4
+vshllbe.u16 q0, q1, #8
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOFP: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOFP: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
--- a/llvm/test/MC/Disassembler/ARM/mve-shifts.txt
+++ b/llvm/test/MC/Disassembler/ARM/mve-shifts.txt
@ -0,0 +1,585 @@
+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vshlc   q0, lr, #8  @ encoding: [0xa8,0xee,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0xce,0x0f]
+
+# CHECK: vmovlb.s8 q0, q6  @ encoding: [0xa8,0xee,0x4c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0x4c,0x0f]
+
+# CHECK: vmovlt.s8 q0, q4  @ encoding: [0xa8,0xee,0x48,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xee,0x48,0x1f]
+
+# CHECK: vmovlb.u8 q0, q0  @ encoding: [0xa8,0xfe,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xfe,0x40,0x0f]
+
+# CHECK: vmovlt.u8 q0, q2  @ encoding: [0xa8,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xfe,0x44,0x1f]
+
+# CHECK: vmovlb.u16 q1, q0  @ encoding: [0xb0,0xfe,0x40,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfe,0x40,0x2f]
+
+# CHECK: vmovlt.u16 q0, q2  @ encoding: [0xb0,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xfe,0x44,0x1f]
+
+# CHECK: vshllb.s8 q0, q2, #8  @ encoding: [0x31,0xee,0x05,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x05,0x0e]
+
+# CHECK: vshllt.s8 q1, q5, #8  @ encoding: [0x31,0xee,0x0b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x0b,0x3e]
+
+# CHECK: vshllb.s8 q0, q0, #7  @ encoding: [0xaf,0xee,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xaf,0xee,0x40,0x0f]
+
+# CHECK: vshllb.u8 q1, q1, #8  @ encoding: [0x31,0xfe,0x03,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x03,0x2e]
+
+# CHECK: vshllt.u8 q0, q0, #8  @ encoding: [0x31,0xfe,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x01,0x1e]
+
+# CHECK: vshllb.u8 q0, q0, #3  @ encoding: [0xab,0xfe,0x40,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xab,0xfe,0x40,0x0f]
+
+# CHECK: vshllb.u16 q0, q5, #16  @ encoding: [0x35,0xfe,0x0b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x0b,0x0e]
+
+# CHECK: vshllt.u16 q0, q3, #16  @ encoding: [0x35,0xfe,0x07,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x07,0x1e]
+
+# CHECK: vshllt.s16 q0, q0, #16  @ encoding: [0x35,0xee,0x01,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x01,0x1e]
+
+# CHECK: vshllt.s16 q0, q0, #14  @ encoding: [0xbe,0xee,0x40,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbe,0xee,0x40,0x1f]
+
+# CHECK: vshllt.s16 q0, q0, #11  @ encoding: [0xbb,0xee,0x40,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbb,0xee,0x40,0x1f]
+
+# CHECK: vshllb.u16 q0, q2, #4  @ encoding: [0xb4,0xfe,0x44,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xfe,0x44,0x0f]
+
+# CHECK: vrshrnb.i16 q0, q3, #1  @ encoding: [0x8f,0xfe,0xc7,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xfe,0xc7,0x0f]
+
+# CHECK: vrshrnt.i16 q0, q2, #5  @ encoding: [0x8b,0xfe,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xfe,0xc5,0x1f]
+
+# CHECK: vrshrnb.i32 q0, q4, #8  @ encoding: [0x98,0xfe,0xc9,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0xc9,0x0f]
+
+# CHECK: vrshrnt.i32 q0, q2, #7  @ encoding: [0x99,0xfe,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0xc5,0x1f]
+
+# CHECK: vshrnb.i16 q1, q2, #1  @ encoding: [0x8f,0xee,0xc5,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0xc5,0x2f]
+
+# CHECK: vshrnt.i16 q0, q1, #1  @ encoding: [0x8f,0xee,0xc3,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0xc3,0x1f]
+
+# CHECK: vshrnb.i32 q0, q0, #12  @ encoding: [0x94,0xee,0xc1,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xee,0xc1,0x0f]
+
+# CHECK: vshrnt.i32 q0, q2, #4  @ encoding: [0x9c,0xee,0xc5,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xee,0xc5,0x1f]
+
+# CHECK: vqrshrunb.s16 q0, q2, #8  @ encoding: [0x88,0xfe,0xc4,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xfe,0xc4,0x0f]
+
+# CHECK: vqrshrunt.s16 q0, q0, #6  @ encoding: [0x8a,0xfe,0xc0,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0xc0,0x1f]
+
+# CHECK: vqrshrunt.s32 q0, q1, #8  @ encoding: [0x98,0xfe,0xc2,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0xc2,0x1f]
+
+# CHECK: vqrshrunb.s32 q0, q7, #13  @ encoding: [0x93,0xfe,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x93,0xfe,0xce,0x0f]
+
+# CHECK: vqshrunb.s16 q0, q7, #5  @ encoding: [0x8b,0xee,0xce,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xee,0xce,0x0f]
+
+# CHECK: vqshrunt.s16 q0, q1, #7  @ encoding: [0x89,0xee,0xc2,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xee,0xc2,0x1f]
+
+# CHECK: vqshrunb.s32 q0, q6, #4  @ encoding: [0x9c,0xee,0xcc,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xee,0xcc,0x0f]
+
+# CHECK: vqshrunt.s32 q0, q2, #10  @ encoding: [0x96,0xee,0xc4,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x96,0xee,0xc4,0x1f]
+
+# CHECK: vqrshrnb.s16 q0, q7, #8  @ encoding: [0x88,0xee,0x4f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xee,0x4f,0x0f]
+
+# CHECK: vqrshrnt.u16 q1, q3, #4  @ encoding: [0x8c,0xfe,0x47,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xfe,0x47,0x3f]
+
+# CHECK: vqrshrnb.u32 q0, q1, #7  @ encoding: [0x99,0xfe,0x43,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x43,0x0f]
+
+# CHECK: vqrshrnt.s32 q0, q1, #11  @ encoding: [0x95,0xee,0x43,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x95,0xee,0x43,0x1f]
+
+# CHECK: vqshrnb.s16 q0, q6, #5  @ encoding: [0x8b,0xee,0x4c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xee,0x4c,0x0f]
+
+# CHECK: vqshrnt.s16 q0, q1, #4  @ encoding: [0x8c,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xee,0x42,0x1f]
+
+# CHECK: vqshrnb.u16 q0, q3, #7  @ encoding: [0x89,0xfe,0x46,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xfe,0x46,0x0f]
+
+# CHECK: vqshrnt.u16 q0, q2, #8  @ encoding: [0x88,0xfe,0x44,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xfe,0x44,0x1f]
+
+# CHECK: vqshrnt.s32 q1, q4, #3  @ encoding: [0x9d,0xee,0x48,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9d,0xee,0x48,0x3f]
+
+# CHECK: vqshrnb.u32 q0, q2, #14  @ encoding: [0x92,0xfe,0x44,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x92,0xfe,0x44,0x0f]
+
+# CHECK: vshl.s8 q6, q6, q6  @ encoding: [0x0c,0xef,0x4c,0xc4]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x4c,0xc4]
+
+# CHECK: vshl.s16 q0, q4, q2  @ encoding: [0x14,0xef,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x48,0x04]
+
+# CHECK: vshl.s32 q1, q1, q5  @ encoding: [0x2a,0xef,0x42,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x42,0x24]
+
+# CHECK: vshl.u8 q1, q7, q2  @ encoding: [0x04,0xff,0x4e,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x4e,0x24]
+
+# CHECK: vshl.u16 q0, q4, q0  @ encoding: [0x10,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xff,0x48,0x04]
+
+# CHECK: vshl.u32 q2, q2, q4  @ encoding: [0x28,0xff,0x44,0x44]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x44,0x44]
+
+# CHECK: vqshl.s8 q0, q1, q6  @ encoding: [0x0c,0xef,0x52,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x52,0x04]
+
+# CHECK: vqshl.s16 q4, q3, q7  @ encoding: [0x1e,0xef,0x56,0x84]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xef,0x56,0x84]
+
+# CHECK: vqshl.s32 q0, q5, q5  @ encoding: [0x2a,0xef,0x5a,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x5a,0x04]
+
+# CHECK: vqshl.u8 q0, q0, q6  @ encoding: [0x0c,0xff,0x50,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xff,0x50,0x04]
+
+# CHECK: vqshl.u16 q0, q5, q4  @ encoding: [0x18,0xff,0x5a,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xff,0x5a,0x04]
+
+# CHECK: vqshl.u32 q1, q0, q4  @ encoding: [0x28,0xff,0x50,0x24]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x50,0x24]
+
+# CHECK: vqrshl.s8 q1, q6, q1  @ encoding: [0x02,0xef,0x5c,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xef,0x5c,0x25]
+
+# CHECK: vqrshl.s16 q2, q4, q6  @ encoding: [0x1c,0xef,0x58,0x45]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xef,0x58,0x45]
+
+# CHECK: vqrshl.s32 q0, q0, q5  @ encoding: [0x2a,0xef,0x50,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xef,0x50,0x05]
+
+# CHECK: vqrshl.u8 q0, q2, q1  @ encoding: [0x02,0xff,0x54,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x54,0x05]
+
+# CHECK: vqrshl.u16 q1, q6, q0  @ encoding: [0x10,0xff,0x5c,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xff,0x5c,0x25]
+
+# CHECK: vqrshl.u32 q0, q0, q0  @ encoding: [0x20,0xff,0x50,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xff,0x50,0x05]
+
+# CHECK: vrshl.s8 q0, q6, q4  @ encoding: [0x08,0xef,0x4c,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x4c,0x05]
+
+# CHECK: vrshl.s16 q1, q4, q7  @ encoding: [0x1e,0xef,0x48,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xef,0x48,0x25]
+
+# CHECK: vrshl.s32 q1, q4, q4  @ encoding: [0x28,0xef,0x48,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xef,0x48,0x25]
+
+# CHECK: vrshl.u8 q0, q3, q5  @ encoding: [0x0a,0xff,0x46,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xff,0x46,0x05]
+
+# CHECK: vrshl.u16 q5, q6, q5  @ encoding: [0x1a,0xff,0x4c,0xa5]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xff,0x4c,0xa5]
+
+# CHECK: vrshl.u32 q1, q7, q3  @ encoding: [0x26,0xff,0x4e,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xff,0x4e,0x25]
+
+# CHECK: vsri.8 q0, q2, #3  @ encoding: [0x8d,0xff,0x54,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8d,0xff,0x54,0x04]
+
+# CHECK: vsri.16 q0, q2, #5  @ encoding: [0x9b,0xff,0x54,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9b,0xff,0x54,0x04]
+
+# CHECK: vsri.32 q0, q1, #15  @ encoding: [0xb1,0xff,0x52,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0x52,0x04]
+
+# CHECK: vsli.8 q0, q3, #3  @ encoding: [0x8b,0xff,0x56,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xff,0x56,0x05]
+
+# CHECK: vsli.16 q0, q1, #12  @ encoding: [0x9c,0xff,0x52,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xff,0x52,0x05]
+
+# CHECK: vsli.32 q0, q1, #8  @ encoding: [0xa8,0xff,0x52,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xff,0x52,0x05]
+
+# CHECK: vqshl.s8 q0, q4, #6  @ encoding: [0x8e,0xef,0x58,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xef,0x58,0x07]
+
+# CHECK: vqshl.u8 q0, q6, #6  @ encoding: [0x8e,0xff,0x5c,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xff,0x5c,0x07]
+
+# CHECK: vqshl.s16 q1, q2, #5  @ encoding: [0x95,0xef,0x54,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x95,0xef,0x54,0x27]
+
+# CHECK: vqshl.u16 q0, q5, #3  @ encoding: [0x93,0xff,0x5a,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x93,0xff,0x5a,0x07]
+
+# CHECK: vqshl.s32 q1, q3, #29  @ encoding: [0xbd,0xef,0x56,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xbd,0xef,0x56,0x27]
+
+# CHECK: vqshl.u32 q0, q2, #19  @ encoding: [0xb3,0xff,0x54,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb3,0xff,0x54,0x07]
+
+# CHECK: vqshlu.s8 q0, q1, #0  @ encoding: [0x88,0xff,0x52,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xff,0x52,0x06]
+
+# CHECK: vqshlu.s16 q2, q1, #12  @ encoding: [0x9c,0xff,0x52,0x46]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xff,0x52,0x46]
+
+# CHECK: vqshlu.s32 q0, q4, #26  @ encoding: [0xba,0xff,0x58,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xff,0x58,0x06]
+
+# CHECK: vrshr.s8 q1, q3, #7  @ encoding: [0x89,0xef,0x56,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xef,0x56,0x22]
+
+# CHECK: vrshr.u8 q1, q3, #2  @ encoding: [0x8e,0xff,0x56,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xff,0x56,0x22]
+
+# CHECK: vrshr.s16 q0, q1, #10  @ encoding: [0x96,0xef,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x96,0xef,0x52,0x02]
+
+# CHECK: vrshr.u16 q0, q5, #12  @ encoding: [0x94,0xff,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x94,0xff,0x5a,0x02]
+
+# CHECK: vrshr.s32 q0, q5, #23  @ encoding: [0xa9,0xef,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa9,0xef,0x5a,0x02]
+
+# CHECK: vrshr.u32 q0, q1, #30  @ encoding: [0xa2,0xff,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xff,0x52,0x02]
+
+# CHECK: vshr.s8 q0, q7, #4  @ encoding: [0x8c,0xef,0x5e,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xef,0x5e,0x00]
+
+# CHECK: vshr.u8 q0, q2, #5  @ encoding: [0x8b,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8b,0xff,0x54,0x00]
+
+# CHECK: vshr.s16 q0, q3, #16  @ encoding: [0x90,0xef,0x56,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x90,0xef,0x56,0x00]
+
+# CHECK: vshr.u16 q7, q6, #8  @ encoding: [0x98,0xff,0x5c,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xff,0x5c,0xe0]
+
+# CHECK: vshr.s32 q0, q6, #24  @ encoding: [0xa8,0xef,0x5c,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa8,0xef,0x5c,0x00]
+
+# CHECK: vshr.u32 q2, q5, #30  @ encoding: [0xa2,0xff,0x5a,0x40]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xff,0x5a,0x40]
+
+# CHECK: vshl.i8 q0, q6, #6  @ encoding: [0x8e,0xef,0x5c,0x05]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xef,0x5c,0x05]
+
+# CHECK: vshl.i16 q1, q0, #12  @ encoding: [0x9c,0xef,0x50,0x25]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x9c,0xef,0x50,0x25]
+
+# CHECK: vshl.i32 q2, q2, #26  @ encoding: [0xba,0xef,0x54,0x45]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xba,0xef,0x54,0x45]
+
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+[0x71,0xfe,0x4d,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstt @ encoding: [0x31,0xfe,0x4d,0x8f]
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+[0x31,0xfe,0x4d,0x8f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x8f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttt @ encoding: [0x31,0xfe,0x4d,0x4f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x4f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstte @ encoding: [0x31,0xfe,0x4d,0xcf]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xcf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xcf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstee @ encoding: [0x71,0xfe,0x4d,0x4f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x4f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+
+# CHECK: vpstttt @ encoding: [0x31,0xfe,0x4d,0x2f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x2f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttte @ encoding: [0x31,0xfe,0x4d,0x6f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x6f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttet @ encoding: [0x31,0xfe,0x4d,0xef]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xef]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsttee @ encoding: [0x31,0xfe,0x4d,0xaf]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0xaf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpstett @ encoding: [0x71,0xfe,0x4d,0xaf]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbt.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xaf]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpstete @ encoding: [0x71,0xfe,0x4d,0xef]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0xef]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+
+# CHECK: vpsteee @ encoding: [0x71,0xfe,0x4d,0x2f]
+# CHECK-NOMVE: [[@LINE+9]]:2: warning: invalid instruction encoding
+# CHECK: vshlltt.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+8]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+7]]:2: warning: invalid instruction encoding
+# CHECK: vshllte.s16 q0, q1, #4 @ encoding: [0xb4,0xee,0x42,0x1f]
+# CHECK-NOMVE: [[@LINE+6]]:2: warning: invalid instruction encoding
+# CHECK: vshllbe.u16 q0, q1, #8 @ encoding: [0xb8,0xfe,0x42,0x0f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+[0x71,0xfe,0x4d,0x2f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]
+[0xb4,0xee,0x42,0x1f]
+[0xb8,0xfe,0x42,0x0f]