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[Hexagon] Run late copy propagation and dead code elimination passes 

llvm-svn: 323346
This commit is contained in:
Krzysztof Parzyszek 2018-01-24 17:48:11 +00:00
parent c30bcad19c
commit cf3ad5841b
11 changed files with 48 additions and 37 deletions
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5
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
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@ -299,6 +299,11 @@ void HexagonPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
bool NoOpt = (getOptLevel() == CodeGenOpt::None);
if (!NoOpt) {
addPass(createConstantPropagationPass());
addPass(createDeadCodeEliminationPass());
}
addPass(createAtomicExpandPass());
if (!NoOpt) {
if (EnableLoopPrefetch)

14
llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll
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@ -6,13 +6,15 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @fred() #0 {
define void @fred(<16 x float>* %a0, <16 x i16>* %a1, <16 x i32>* %a2) #0 {
b0:
%v1 = fcmp olt <16 x float> zeroinitializer, undef
%v2 = select <16 x i1> %v1, <16 x i16> undef, <16 x i16> zeroinitializer
%v3 = sext <16 x i16> %v2 to <16 x i32>
store <16 x i32> %v3, <16 x i32>* undef, align 128
unreachable
%v0 = load <16 x float>, <16 x float>* %a0, align 128
%v1 = fcmp olt <16 x float> zeroinitializer, %v0
%v2 = load <16 x i16>, <16 x i16>* %a1, align 128
%v3 = select <16 x i1> %v1, <16 x i16> %v2, <16 x i16> zeroinitializer
%v4 = sext <16 x i16> %v3 to <16 x i32>
store <16 x i32> %v4, <16 x i32>* %a2, align 128
ret void
}
attributes #0 = { noinline norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b" }

9
llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
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@ -6,11 +6,12 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @fred() #0 {
define void @fred(<8 x float>* %a0, <8 x float>* %a1) #0 {
b0:
%v1 = fcmp olt <8 x float> undef, zeroinitializer
%v2 = load <8 x float>, <8 x float>* null, align 8
%v3 = fcmp olt <8 x float> %v2, undef
%v0 = load <8 x float>, <8 x float>* %a1, align 8
%v1 = fcmp olt <8 x float> %v0, zeroinitializer
%v2 = load <8 x float>, <8 x float>* %a0, align 8
%v3 = fcmp olt <8 x float> %v2, zeroinitializer
%v4 = and <8 x i1> %v1, %v3
%v5 = zext <8 x i1> %v4 to <8 x i32>
store <8 x i32> %v5, <8 x i32>* undef, align 8

5
llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll
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@ -7,9 +7,10 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i
target triple = "hexagon"
; Function Attrs: norecurse nounwind
define void @fred() #0 {
define void @fred(<16 x i32> %a0, <16 x i32> %a1) #0 {
b0:
%v1 = select <16 x i1> undef, <16 x i32> undef, <16 x i32> zeroinitializer
%v0 = icmp eq <16 x i32> %a0, %a1
%v1 = select <16 x i1> %v0, <16 x i32> %a0, <16 x i32> zeroinitializer
%v2 = trunc <16 x i32> %v1 to <16 x i16>
store <16 x i16> %v2, <16 x i16>* undef, align 2
ret void

8
llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll
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@ -6,9 +6,9 @@ target triple = "hexagon"
; CHECK-LABEL: danny:
; CHECK: vunpack
; CHECK-NOT: vinsert
define void @danny() local_unnamed_addr #0 {
define void @danny(<16 x i16>* %a0) local_unnamed_addr #0 {
b2:
%v16 = select <16 x i1> undef, <16 x i16> undef, <16 x i16> zeroinitializer
%v16 = load <16 x i16>, <16 x i16>* %a0, align 128
%v17 = sext <16 x i16> %v16 to <16 x i32>
store <16 x i32> %v17, <16 x i32>* undef, align 128
unreachable
@ -17,9 +17,9 @@ b2:
; CHECK-LABEL: sammy:
; CHECK: vunpack
; CHECK-NOT: vinsert
define void @sammy() local_unnamed_addr #1 {
define void @sammy(<32 x i16>* %a0) local_unnamed_addr #1 {
b2:
%v16 = select <32 x i1> undef, <32 x i16> undef, <32 x i16> zeroinitializer
%v16 = load <32 x i16>, <32 x i16>* %a0, align 128
%v17 = sext <32 x i16> %v16 to <32 x i32>
store <32 x i32> %v17, <32 x i32>* undef, align 128
unreachable

4
llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll
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@ -10,9 +10,9 @@ target triple = "hexagon"
%struct.0 = type { i16, i16 }
; Function Attrs: nounwind
define i16 @TraceBack() #0 {
define i16 @TraceBack(%struct.0* %t) #0 {
entry:
%p = getelementptr inbounds %struct.0, %struct.0* undef, i32 0, i32 0
%p = getelementptr inbounds %struct.0, %struct.0* %t, i32 0, i32 0
%a = load i16, i16* %p
ret i16 %a
}

8
llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll
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@ -7,9 +7,9 @@ target triple = "hexagon"
; CHECK-LABEL: danny:
; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
; CHECK-DAG: if (![[PREG]]) [[VREG]]
define void @danny() local_unnamed_addr #0 {
define void @danny(i32 %a0) local_unnamed_addr #0 {
b0:
%v1 = icmp eq i32 0, undef
%v1 = icmp eq i32 0, %a0
%v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> undef
%v3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v2, <16 x i32> zeroinitializer, i32 2)
%v4 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %v3)
@ -29,9 +29,9 @@ declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #2
; CHECK-LABEL: sammy:
; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
; CHECK-DAG: if (![[PREG]]) [[VREG]]
define void @sammy() local_unnamed_addr #1 {
define void @sammy(i32 %a0) local_unnamed_addr #1 {
b0:
%v1 = icmp eq i32 0, undef
%v1 = icmp eq i32 0, %a0
%v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> undef
%v3 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %v2, <32 x i32> zeroinitializer, i32 2)
%v4 = tail call <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3)

9
llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll
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@ -7,9 +7,8 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @fred(i16 signext %a0) #0 {
define void @fred(i16 signext %a0, <32 x i16>* %a1, <32 x i16> %a3) #0 {
b1:
%v2 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> zeroinitializer
%v4 = add i16 undef, %a0
br i1 undef, label %b11, label %b5
@ -17,10 +16,10 @@ b5: ; preds = %b1
%v6 = insertelement <32 x i16> undef, i16 %v4, i32 0
%v7 = shufflevector <32 x i16> %v6, <32 x i16> undef, <32 x i32> zeroinitializer
%v8 = add <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31>, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
%v9 = mul <32 x i16> %v8, %v2
%v9 = mul <32 x i16> %v8, %a3
%v10 = add <32 x i16> %v7, %v9
store <32 x i16> %v10, <32 x i16>* undef, align 2
unreachable
store <32 x i16> %v10, <32 x i16>* %a1, align 2
ret void
b11: ; preds = %b1
unreachable

7
llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll
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@ -8,10 +8,11 @@ target triple = "hexagon"
@g0 = external hidden unnamed_addr global [182 x i16], align 8
define void @fred(i16 signext %a0) local_unnamed_addr #0 {
define void @fred(i16 signext %a0, i16 signext %a1) #0 {
b1:
%v2 = getelementptr inbounds [182 x i16], [182 x i16]* @g0, i32 0, i32 0
%v3 = sext i16 %a0 to i32
%v1 = sext i16 %a0 to i32
%v2 = getelementptr inbounds [182 x i16], [182 x i16]* @g0, i32 0, i32 %v1
%v3 = sext i16 %a1 to i32
%v4 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
%v5 = trunc i32 %v4 to i16
br i1 undef, label %b6, label %b14

11
llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll
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@ -16,9 +16,9 @@ declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32)
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1
declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
define hidden void @fred() #0 {
define hidden void @fred(<32 x i32>* %a0, i32 %a1) #0 {
b0:
%v1 = ashr i32 undef, 7
%v1 = ashr i32 %a1, 7
%v2 = shl nsw i32 %v1, 7
switch i32 undef, label %b7 [
i32 1, label %b3
@ -80,7 +80,8 @@ b18: ; preds = %b16
br label %b19
b19: ; preds = %b18
br i1 undef, label %b20, label %b21
%v21 = icmp sgt i32 %a1, 0
br i1 %v21, label %b20, label %b21
b20: ; preds = %b19
br label %b32
@ -90,7 +91,7 @@ b21: ; preds = %b38, %b19
%v23 = lshr i64 %v22, 31
%v24 = shl nuw nsw i64 %v23, 1
%v25 = or i64 %v24, 0
%v26 = icmp ult i64 undef, 2147483648
%v26 = icmp ult i64 %v23, 2147483648
%v27 = mul nuw nsw i64 %v25, 3
%v28 = add nuw nsw i64 %v27, 0
%v29 = and i64 %v28, 133143986176
@ -134,7 +135,7 @@ b42: ; preds = %b40
%v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2
%v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2
%v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2
store <32 x i32> %v54, <32 x i32>* undef, align 128
store <32 x i32> %v54, <32 x i32>* %a0, align 128
br label %b39
}

5
llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll
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@ -6,7 +6,7 @@
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define void @fred() #0 {
define void @fred(<8 x i16>* %a0) #0 {
b0:
switch i32 undef, label %b14 [
i32 5, label %b2
@ -17,7 +17,8 @@ b1: ; preds = %b0
br label %b14
b2: ; preds = %b0
%v3 = icmp eq <8 x i16> undef, zeroinitializer
%v2 = load <8 x i16>, <8 x i16>* %a0, align 64
%v3 = icmp eq <8 x i16> %v2, zeroinitializer
%v4 = zext <8 x i1> %v3 to <8 x i16>
%v5 = add <8 x i16> zeroinitializer, %v4
%v6 = add <8 x i16> %v5, zeroinitializer