From cef9d42157e568eb1d87208be630a4185c675a26 Mon Sep 17 00:00:00 2001
From: Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>
Date: Mon, 8 Jul 2019 16:50:11 +0000
Subject: [PATCH] [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax
 description.

Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.

llvm-svn: 365347
---
 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst           | 2176 +++++++++++++++++
 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst            |  532 ++--
 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst            |  641 ++---
 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst            |  781 +++---
 llvm/docs/AMDGPU/gfx10_addr_buf.rst           |   22 +
 llvm/docs/AMDGPU/gfx10_addr_ds.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_addr_flat.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_addr_mimg.rst          |   23 +
 llvm/docs/AMDGPU/gfx10_attr.rst               |   30 +
 llvm/docs/AMDGPU/gfx10_base_smem_addr.rst     |   17 +
 llvm/docs/AMDGPU/gfx10_base_smem_buf.rst      |   17 +
 llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst  |   17 +
 llvm/docs/AMDGPU/gfx10_bimm16.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_bimm32.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst |   21 +
 llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst  |   21 +
 llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst  |   21 +
 .../AMDGPU/gfx10_data_mimg_atomic_cmp.rst     |   27 +
 .../AMDGPU/gfx10_data_mimg_atomic_reg.rst     |   26 +
 llvm/docs/AMDGPU/gfx10_data_mimg_store.rst    |   18 +
 .../docs/AMDGPU/gfx10_data_mimg_store_d16.rst |   21 +
 .../docs/AMDGPU/gfx10_data_smem_atomic128.rst |   21 +
 llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst |   21 +
 llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst |   21 +
 llvm/docs/AMDGPU/gfx10_dst_buf_128.rst        |   17 +
 llvm/docs/AMDGPU/gfx10_dst_buf_32.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_dst_buf_64.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_dst_buf_96.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst        |   21 +
 llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst  |   19 +
 llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst  |   19 +
 llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst   |   22 +
 llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst   |   20 +
 .../AMDGPU/gfx10_dst_mimg_regular_d16.rst     |   22 +
 llvm/docs/AMDGPU/gfx10_fimm16.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_fimm32.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_hwreg.rst              |   69 +
 llvm/docs/AMDGPU/gfx10_label.rst              |   30 +
 llvm/docs/AMDGPU/gfx10_mad_type_dev.rst       |   17 +
 .../AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst     |   14 +
 llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst      |   14 +
 llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst   |   14 +
 llvm/docs/AMDGPU/gfx10_msg.rst                |   73 +
 llvm/docs/AMDGPU/gfx10_offset_buf.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst    |   19 +
 llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst  |   22 +
 llvm/docs/AMDGPU/gfx10_opt.rst                |   14 +
 llvm/docs/AMDGPU/gfx10_param.rst              |   22 +
 llvm/docs/AMDGPU/gfx10_perm_smem.rst          |   24 +
 llvm/docs/AMDGPU/gfx10_ret.rst                |   14 +
 llvm/docs/AMDGPU/gfx10_rsrc_buf.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst  |   19 +
 llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst |   19 +
 llvm/docs/AMDGPU/gfx10_samp_mimg.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdata128_0.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_sdata32_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdata64_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdst128_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdst256_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdst32_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_sdst32_1.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_sdst32_2.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_sdst512_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_sdst64_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_sdst64_1.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_simm16.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_src32_0.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src32_1.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src32_2.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src32_3.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src64_0.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src_exp.rst            |   28 +
 llvm/docs/AMDGPU/gfx10_ssrc32_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc32_1.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc32_2.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc32_3.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc32_4.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc32_5.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc64_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc64_1.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_tgt.rst                |   25 +
 llvm/docs/AMDGPU/gfx10_type_dev.rst           |   14 +
 llvm/docs/AMDGPU/gfx10_uimm16.rst             |   14 +
 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst  |   22 +
 llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst |   19 +
 llvm/docs/AMDGPU/gfx10_vcc_32.rst             |   17 +
 llvm/docs/AMDGPU/gfx10_vdata128_0.rst         |   17 +
 llvm/docs/AMDGPU/gfx10_vdata32_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_vdata64_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_vdata96_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_vdst128_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_vdst32_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_vdst64_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_vdst96_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_vsrc128_0.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_vsrc32_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_vsrc32_1.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_vsrc64_0.rst           |   17 +
 llvm/docs/AMDGPU/gfx10_waitcnt.rst            |   56 +
 llvm/docs/AMDGPU/gfx10_wsdst.rst              |   17 +
 llvm/docs/AMDGPU/gfx10_wssrc.rst              |   17 +
 llvm/docs/AMDGPU/gfx7_offset_buf.rst          |    2 +-
 llvm/docs/AMDGPU/gfx7_src32_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src32_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src32_2.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src32_3.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src32_4.rst             |   17 +
 llvm/docs/AMDGPU/gfx7_src32_5.rst             |   17 +
 llvm/docs/AMDGPU/gfx7_src32_6.rst             |   17 +
 llvm/docs/AMDGPU/gfx7_src64_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src64_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_src64_2.rst             |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc32_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc32_1.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc32_3.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc32_4.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc32_5.rst            |   17 +
 llvm/docs/AMDGPU/gfx7_ssrc32_6.rst            |   17 +
 llvm/docs/AMDGPU/gfx7_ssrc64_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_ssrc64_2.rst            |    2 +-
 llvm/docs/AMDGPU/gfx7_vsrc32_1.rst            |   17 +
 llvm/docs/AMDGPU/gfx8_offset_buf.rst          |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_2.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_src32_3.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_src64_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src64_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_ssrc32_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx8_ssrc32_4.rst            |    2 +-
 llvm/docs/AMDGPU/gfx8_ssrc64_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx8_ssrc64_2.rst            |    2 +-
 llvm/docs/AMDGPU/gfx8_vsrc32_1.rst            |   17 +
 llvm/docs/AMDGPU/gfx9_msg.rst                 |    1 +
 llvm/docs/AMDGPU/gfx9_offset_buf.rst          |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_2.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_src32_3.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_src64_0.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src64_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_ssrc32_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx9_ssrc32_4.rst            |    2 +-
 llvm/docs/AMDGPU/gfx9_ssrc64_0.rst            |    2 +-
 llvm/docs/AMDGPU/gfx9_ssrc64_2.rst            |    2 +-
 llvm/docs/AMDGPU/gfx9_vsrc32_1.rst            |   17 +
 llvm/docs/AMDGPUInstructionSyntax.rst         |    2 +
 llvm/docs/AMDGPUModifierSyntax.rst            |  349 ++-
 llvm/docs/AMDGPUOperandSyntax.rst             |  113 +-
 llvm/docs/AMDGPUUsage.rst                     |    7 +-
 151 files changed, 5713 insertions(+), 1089 deletions(-)
 create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_addr_buf.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_addr_ds.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_addr_flat.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_addr_mimg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_attr.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_base_smem_addr.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_base_smem_buf.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_bimm16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_bimm32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_store.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_128.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_64.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_96.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_fimm16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_fimm32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_hwreg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_label.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_msg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_offset_buf.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_opt.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_param.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_perm_smem.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ret.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_rsrc_buf.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_samp_mimg.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdata128_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdata32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdata64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst128_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst256_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst512_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_sdst64_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_simm16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src_exp.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_tgt.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_type_dev.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_uimm16.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vcc_32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdata128_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdata32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdata64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdata96_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdst128_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdst32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdst64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vdst96_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vsrc128_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vsrc32_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vsrc32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_vsrc64_0.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_waitcnt.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_wsdst.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_wssrc.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_src32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_src32_6.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_ssrc32_6.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_vsrc32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_vsrc32_1.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_vsrc32_1.rst

diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
new file mode 100644
index 000000000000..033a16355672
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
@@ -0,0 +1,2176 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+============================
+Syntax of GFX10 Instructions
+============================
+
+.. contents::
+  :local:
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Introduction
+============
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DPP16
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**             **DST0**  **DST1** **SRC0**       **SRC1**      **SRC2**   **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_ci_u32_dpp     :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`    :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_add_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_add_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_add_nc_u32_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_and_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ashrrev_i32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_bfrev_b32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ceil_f16_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ceil_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cos_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cos_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f16_f32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f16_i16_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f16_u16_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_f16_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_i32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_u32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_ubyte0_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_ubyte1_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_ubyte2_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_f32_ubyte3_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_flr_i32_f32_dpp   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_i16_f16_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_i32_f32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_norm_i16_f16_dpp  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_norm_u16_f16_dpp  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_off_f32_i4_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_rpi_i32_f32_dpp   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_u16_f16_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cvt_u32_f32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_exp_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_exp_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ffbh_i32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ffbh_u32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ffbl_b32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_floor_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_floor_f32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_fmac_f16_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_fmac_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_fract_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_fract_f32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_frexp_mant_f16_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_frexp_mant_f32_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_ldexp_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_log_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_log_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_lshlrev_b32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_lshrrev_b32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mac_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_max_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_max_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_max_i32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_max_u32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_min_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_min_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_min_i32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_min_u32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mov_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_hi_i32_i24_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_hi_u32_u24_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_i32_i24_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_legacy_f32_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_mul_u32_u24_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_not_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_or_b32_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rcp_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rcp_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rcp_iflag_f32_dpp     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rndne_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rndne_f32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rsq_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_rsq_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sat_pk_u8_i16_dpp     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sin_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sin_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sqrt_f16_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sqrt_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sub_co_ci_u32_dpp     :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`    :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sub_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sub_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_sub_nc_u32_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_subrev_co_ci_u32_dpp  :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`    :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_subrev_f16_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_subrev_f32_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_subrev_nc_u32_dpp     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_trunc_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_trunc_f32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_xnor_b32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_xor_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+
+DPP8
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_ci_u32_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_add_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_add_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_add_nc_u32_dpp               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_and_b32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ashrrev_i32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_bfrev_b32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ceil_f16_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ceil_f32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cos_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cos_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f16_f32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f16_i16_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f16_u16_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_f16_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_i32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_u32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_ubyte0_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_ubyte1_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_ubyte2_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_f32_ubyte3_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_flr_i32_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_i16_f16_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_i32_f32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_norm_i16_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_norm_u16_f16_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_off_f32_i4_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_rpi_i32_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_u16_f16_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cvt_u32_f32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_exp_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_exp_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ffbh_i32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ffbh_u32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ffbl_b32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_floor_f16_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_floor_f32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_fmac_f16_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_fmac_f32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_fract_f16_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_fract_f32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_frexp_exp_i16_f16_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_frexp_exp_i32_f32_dpp        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_frexp_mant_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_frexp_mant_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_ldexp_f16_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_log_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_log_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_lshlrev_b32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_lshrrev_b32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mac_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_max_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_max_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_max_i32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_max_u32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_min_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_min_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_min_i32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_min_u32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mov_b32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_hi_i32_i24_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_hi_u32_u24_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_i32_i24_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_legacy_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_mul_u32_u24_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_not_b32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_or_b32_dpp                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rcp_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rcp_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rcp_iflag_f32_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rndne_f16_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rndne_f32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rsq_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_rsq_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sat_pk_u8_i16_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sin_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sin_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sqrt_f16_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sqrt_f32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sub_co_ci_u32_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sub_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sub_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_sub_nc_u32_dpp               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_subrev_co_ci_u32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_subrev_f16_dpp               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_subrev_f32_dpp               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_subrev_nc_u32_dpp            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_trunc_f16_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_trunc_f32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_xnor_b32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_xor_b32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+
+DS
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**         **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_add_f32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_f32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_f32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_add_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_b64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_rtn_b64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_and_src2_b64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_append                      :ref:`vdst<amdgpu_synid10_vdst32_0>`                                           :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_bpermute_b32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>`
+    ds_cmpst_b32                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_b64                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f32                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_f64                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_b64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_cmpst_rtn_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_condxchg32_rtn_b64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_consume                     :ref:`vdst<amdgpu_synid10_vdst32_0>`                                           :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_dec_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_barrier                             :ref:`vdata<amdgpu_synid10_vdata32_0>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_init                                :ref:`vdata<amdgpu_synid10_vdata32_0>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_br                             :ref:`vdata<amdgpu_synid10_vdata32_0>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_p                                                                 :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_release_all                                                       :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_gws_sema_v                                                                 :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_inc_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_f64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_i64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_f64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_i64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_f64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_i64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_max_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_f64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_i64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_f64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_i64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_f64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_i64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_min_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b32                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_b64                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_mskor_rtn_b64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_nop
+    ds_or_b32                                  :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_b64                                  :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_rtn_b64                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b32                             :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_or_src2_b64                             :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_ordered_count               :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_permute_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>`
+    ds_read2_b32                   :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2_b64                   :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b32               :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read2st64_b64               :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b128                   :ref:`vdst<amdgpu_synid10_vdst128_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_b96                    :ref:`vdst<amdgpu_synid10_vdst96_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_i8_d16_hi              :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u16_d16_hi             :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_u8_d16_hi              :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_rtn_u64                :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u32                           :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_src2_u64                           :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u32                                :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_rsub_u64                                :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_rtn_u64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_src2_u64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_sub_u64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_swizzle_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrap_rtn_b32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b32                              :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2_b64                              :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b128                              :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b16_d16_hi                        :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b32                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b64                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8                                :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b8_d16_hi                         :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_b96                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b32                          :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_src2_b64                          :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b32             :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2_rtn_b64             :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b32         :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg2st64_rtn_b64         :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_wrxchg_rtn_b64              :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b32                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_b64                                 :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_rtn_b64                 :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b32                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+    ds_xor_src2_b64                            :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    exp                            :ref:`tgt<amdgpu_synid10_tgt>`,      :ref:`vsrc0<amdgpu_synid10_src_exp>`,    :ref:`vsrc1<amdgpu_synid10_src_exp>`,    :ref:`vsrc2<amdgpu_synid10_src_exp>`,    :ref:`vsrc3<amdgpu_synid10_src_exp>`          :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**         **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    flat_atomic_add                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_add_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_and_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap            :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_cmpswap_x2         :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_dec_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap           :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f32x2<amdgpu_synid10_type_dev>`                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fcmpswap_x2        :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`f64x2<amdgpu_synid10_type_dev>`                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmax_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_fmin_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_inc_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or                 :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_or_x2              :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smax_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_smin_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_sub_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_swap_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umax_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_umin_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor                :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_atomic_xor_x2             :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    flat_load_dword                :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_dwordx2              :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_dwordx3              :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_dwordx4              :ref:`vdst<amdgpu_synid10_vdst128_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_sbyte                :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_sbyte_d16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_sbyte_d16_hi         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_short_d16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_short_d16_hi         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_sshort               :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_ubyte                :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_ubyte_d16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_ubyte_d16_hi         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_load_ushort               :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_addr_flat>`                                 :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_byte                              :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_byte_d16_hi                       :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_dword                             :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_dwordx2                           :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_dwordx3                           :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_short                             :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    flat_store_short_d16_hi                      :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_atomic_add              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_add_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_and              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_and_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_cmpswap          :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_cmpswap_x2       :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_dec              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_dec_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_fmax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_fmax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_fmin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_fmin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_inc              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_inc_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_or               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_or_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_smax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_smax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_smin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_smin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_sub              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_sub_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_swap             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_swap_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_umax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_umax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_umin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_umin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_xor              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_xor_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_dword              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_dwordx2            :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_dwordx3            :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_dwordx4            :ref:`vdst<amdgpu_synid10_vdst128_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_sbyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_sbyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_short_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_short_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_sshort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_ubyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_ubyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_load_ushort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_byte                            :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_byte_d16_hi                     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_dword                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_dwordx2                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_dwordx3                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_dwordx4                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_short                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_store_short_d16_hi                    :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    scratch_load_dword             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_dwordx2           :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_dwordx3           :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_dwordx4           :ref:`vdst<amdgpu_synid10_vdst128_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_sbyte             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_sbyte_d16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_sbyte_d16_hi      :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_short_d16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_short_d16_hi      :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_sshort            :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_ubyte             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_ubyte_d16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_ubyte_d16_hi      :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_load_ushort            :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_byte                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_byte_d16_hi                    :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_dword                          :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_dwordx2                        :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_dwordx3                        :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_dwordx4                        :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_short                          :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    scratch_store_short_d16_hi                   :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+
+MIMG
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**            **DST**      **SRC0**       **SRC1**     **SRC2**       **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_and                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_cmpswap            :ref:`vdata<amdgpu_synid10_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_dec                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_inc                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_or                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_smax               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_smin               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_sub                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_swap               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_umax               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_umin               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_xor                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_gather4          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o    :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o    :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod          :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_get_resinfo      :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck     :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_pck         :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_pck_sgn     :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_sample           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o  :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o  :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                     :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                 :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip_pck             :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_store_pck                 :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+
+MUBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                  **DST**   **SRC0**             **SRC1**   **SRC2**    **SRC3**    **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2           :ref:`vdata<amdgpu_synid10_data_buf_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or                   :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2                :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_gl0_inv
+    buffer_gl1_inv
+    buffer_load_dword            :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_dwordx2          :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_dwordx3          :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_dwordx4          :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_d16_x     :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_d16_xy    :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_d16_xyz   :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_d16_xyzw  :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_x         :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_xy        :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_xyz       :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_format_xyzw      :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_sbyte            :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_sbyte_d16        :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_sbyte_d16_hi     :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_short_d16        :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_short_d16_hi     :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_sshort           :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_ubyte            :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_ubyte_d16        :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_ubyte_d16_hi     :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_load_ushort           :ref:`vdst<amdgpu_synid10_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`,           :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` :ref:`dlc<amdgpu_synid_dlc>`
+    buffer_store_byte                  :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_byte_d16_hi           :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword                 :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2               :ref:`vdata<amdgpu_synid10_vdata64_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3               :ref:`vdata<amdgpu_synid10_vdata96_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4               :ref:`vdata<amdgpu_synid10_vdata128_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_x          :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xy         :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyz        :ref:`vdata<amdgpu_synid10_vdata64_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_d16_xyzw       :ref:`vdata<amdgpu_synid10_vdata64_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x              :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy             :ref:`vdata<amdgpu_synid10_vdata64_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz            :ref:`vdata<amdgpu_synid10_vdata96_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw           :ref:`vdata<amdgpu_synid10_vdata128_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short                 :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short_d16_hi          :ref:`vdata<amdgpu_synid10_vdata32_0>`,           :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+SDWA
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**              **DST0**  **DST1** **SRC0**        **SRC1**       **SRC2** **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_ci_u32_sdwa     :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`  :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_nc_u32_sdwa        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_and_b32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_bfrev_b32_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f16_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ceil_f32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cmp_class_f16_sdwa     :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_class_f32_sdwa     :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f16_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_f32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lg_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_neq_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nge_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ngt_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nle_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlg_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_nlt_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f16_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_o_f32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_tru_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f16_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_u_f32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f16_sdwa               :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_class_f32_sdwa               :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f16_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_f32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lg_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_neq_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nge_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ngt_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nle_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlg_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_nlt_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f16_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_o_f32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_tru_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f16_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_u_f32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cos_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cos_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_f32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_i32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_u32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte0_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte1_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte2_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f32_ubyte3_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_flr_i32_f32_sdwa   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i16_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_i32_f32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_i16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_u16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_off_f32_i4_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_rpi_i32_f32_sdwa   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u16_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_u32_f32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_exp_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_i32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbh_u32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ffbl_b32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f16_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_floor_f32_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f16_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_fract_f32_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f16_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_frexp_mant_f32_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_ldexp_f16_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`i16<amdgpu_synid10_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_log_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_log_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_lshlrev_b32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mov_b32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_mul_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_i32_i24_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_hi_u32_u24_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_i32_i24_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_legacy_f32_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_u32_u24_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_not_b32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_or_b32_sdwa            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_rcp_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rcp_iflag_f32_sdwa     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f16_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rndne_f32_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_rsq_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sat_pk_u8_i16_sdwa     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sin_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f16_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sqrt_f32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_sub_co_ci_u32_sdwa     :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`  :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_nc_u32_sdwa        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_co_ci_u32_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`, :ref:`vcc<amdgpu_synid10_vcc_32>`, :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`  :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16_sdwa        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32_sdwa        :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_nc_u32_sdwa     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_trunc_f16_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_trunc_f32_sdwa         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_xnor_b32_sdwa          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_xor_b32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+SMEM
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_atc_probe                              :ref:`imm3<amdgpu_synid10_perm_smem>`,            :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+    s_atc_probe_buffer                       :ref:`imm3<amdgpu_synid10_perm_smem>`,            :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`
+    s_atomic_add                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_add_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_and                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_and_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_cmpswap                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_cmpswap_x2                      :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_dec                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_dec_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_inc                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_inc_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_or                              :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_or_x2                           :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smax                            :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smax_x2                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smin                            :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_smin_x2                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_sub                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_sub_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_swap                            :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_swap_x2                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umax                            :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umax_x2                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umin                            :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_umin_x2                         :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_xor                             :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_atomic_xor_x2                          :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_add                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_add_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_and                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_and_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_cmpswap                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_cmpswap_x2               :ref:`sdata<amdgpu_synid10_data_smem_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_dec                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_dec_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_inc                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_inc_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_or                       :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_or_x2                    :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smax                     :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smax_x2                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smin                     :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_smin_x2                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_sub                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_sub_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_swap                     :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_swap_x2                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umax                     :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umax_x2                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umin                     :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_umin_x2                  :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_xor                      :ref:`sdata<amdgpu_synid10_data_smem_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_atomic_xor_x2                   :ref:`sdata<amdgpu_synid10_data_smem_atomic64>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_load_dword            :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_buf>`,           :ref:`soffset<amdgpu_synid10_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_buffer_load_dwordx16         :ref:`sdst<amdgpu_synid10_sdst512_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_buf>`,           :ref:`soffset<amdgpu_synid10_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_buffer_load_dwordx2          :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_buf>`,           :ref:`soffset<amdgpu_synid10_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_buffer_load_dwordx4          :ref:`sdst<amdgpu_synid10_sdst128_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_buf>`,           :ref:`soffset<amdgpu_synid10_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_buffer_load_dwordx8          :ref:`sdst<amdgpu_synid10_sdst256_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_buf>`,           :ref:`soffset<amdgpu_synid10_offset_smem_buf>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_buffer_store_dword                     :ref:`sdata<amdgpu_synid10_sdata32_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx2                   :ref:`sdata<amdgpu_synid10_sdata64_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_buffer_store_dwordx4                   :ref:`sdata<amdgpu_synid10_sdata128_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_buf>`,    :ref:`soffset<amdgpu_synid10_offset_smem_buf>`        :ref:`glc<amdgpu_synid_glc>`
+    s_dcache_discard                         :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+    s_dcache_discard_x2                      :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`
+    s_dcache_inv
+    s_dcache_wb
+    s_get_waveid_in_workgroup      :ref:`sdst<amdgpu_synid10_sdst32_0>`
+    s_gl1_inv
+    s_load_dword                   :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_load_dwordx16                :ref:`sdst<amdgpu_synid10_sdst512_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_load_dwordx2                 :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_load_dwordx4                 :ref:`sdst<amdgpu_synid10_sdst128_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_load_dwordx8                 :ref:`sdst<amdgpu_synid10_sdst256_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_addr>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_memrealtime                  :ref:`sdst<amdgpu_synid10_sdst64_0>`
+    s_memtime                      :ref:`sdst<amdgpu_synid10_sdst64_0>`
+    s_scratch_load_dword           :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_scratch_load_dwordx2         :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_scratch_load_dwordx4         :ref:`sdst<amdgpu_synid10_sdst128_0>`,     :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,           :ref:`soffset<amdgpu_synid10_offset_smem_plain>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+    s_scratch_store_dword                    :ref:`sdata<amdgpu_synid10_sdata32_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_store_dwordx2                  :ref:`sdata<amdgpu_synid10_sdata64_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_scratch_store_dwordx4                  :ref:`sdata<amdgpu_synid10_sdata128_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_scratch>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dword                            :ref:`sdata<amdgpu_synid10_sdata32_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx2                          :ref:`sdata<amdgpu_synid10_sdata64_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+    s_store_dwordx4                          :ref:`sdata<amdgpu_synid10_sdata128_0>`,           :ref:`sbase<amdgpu_synid10_base_smem_addr>`,    :ref:`soffset<amdgpu_synid10_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
+
+SOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_abs_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_and_saveexec_b32             :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_andn1_saveexec_b32           :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_andn1_saveexec_b64           :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_andn1_wrexec_b32             :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_andn1_wrexec_b64             :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_andn2_saveexec_b32           :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_andn2_saveexec_b64           :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_andn2_wrexec_b32             :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_andn2_wrexec_b64             :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_bitreplicate_b64_b32         :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_bitset0_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_bitset0_b64                  :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    s_bitset1_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_bitset1_b64                  :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    s_brev_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_brev_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_cmov_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_cmov_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_ff0_i32_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_ff0_i32_b64                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_ff1_i32_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_ff1_i32_b64                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_flbit_i32                    :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_flbit_i32_b32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_flbit_i32_b64                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_flbit_i32_i64                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_getpc_b64                    :ref:`sdst<amdgpu_synid10_sdst64_1>`
+    s_mov_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_mov_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_movreld_b32                  :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_movreld_b64                  :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_movrels_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+    s_movrels_b64                  :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+    s_movrelsd_2_b32               :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_1>`
+    s_nand_saveexec_b32            :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_nor_saveexec_b32             :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_not_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_not_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_or_saveexec_b32              :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_orn1_saveexec_b32            :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_orn1_saveexec_b64            :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_orn2_saveexec_b32            :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_orn2_saveexec_b64            :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_quadmask_b32                 :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_quadmask_b64                 :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_rfe_b64                                :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+    s_setpc_b64                              :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_swappc_b64                   :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_1>`
+    s_wqm_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_wqm_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_xnor_saveexec_b32            :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+    s_xor_saveexec_b32             :ref:`sdst<amdgpu_synid10_sdst32_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc32_0>`
+    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid10_sdst64_0>`,     :ref:`ssrc<amdgpu_synid10_ssrc64_0>`
+
+SOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**         **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_absdiff_i32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_add_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_add_u32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_addc_u32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_and_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_and_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_andn2_b32                    :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_andn2_b64                    :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_ashr_i32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_ashr_i64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_bfe_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_bfe_i64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_bfe_u32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_bfe_u64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_bfm_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_bfm_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    s_cselect_b32                  :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cselect_b64                  :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_lshl1_add_u32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_lshl2_add_u32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_lshl3_add_u32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_lshl4_add_u32                :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_lshl_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_lshl_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_lshr_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_lshr_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_max_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_max_u32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_min_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_min_u32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_mul_hi_i32                   :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_mul_hi_u32                   :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_mul_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_nand_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_nand_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_nor_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_nor_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_or_b32                       :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_or_b64                       :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_orn2_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_orn2_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_pack_hh_b32_b16              :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`, :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+    s_pack_lh_b32_b16              :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`b16x2<amdgpu_synid10_type_dev>`
+    s_pack_ll_b32_b16              :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_sub_i32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_sub_u32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_subb_u32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_xnor_b32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_xnor_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_xor_b32                      :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_xor_b64                      :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+
+SOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`::ref:`u32<amdgpu_synid10_type_dev>`
+    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_eq_u64                   :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid10_ssrc64_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc64_0>`
+    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid10_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid10_ssrc32_0>`
+
+SOPK
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_addk_i32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_call_b64                     :ref:`sdst<amdgpu_synid10_sdst64_1>`,     :ref:`label<amdgpu_synid10_label>`
+    s_cmovk_i32                    :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_uimm16>`
+    s_getreg_b32                   :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`hwreg<amdgpu_synid10_hwreg>`
+    s_movk_i32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_mulk_i32                     :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`imm16<amdgpu_synid10_simm16>`
+    s_setreg_b32                   :ref:`hwreg<amdgpu_synid10_hwreg>`,    :ref:`ssrc<amdgpu_synid10_ssrc32_2>`
+    s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid10_hwreg>`,    :ref:`imm32<amdgpu_synid10_bimm32>`
+    s_subvector_loop_begin         :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`label<amdgpu_synid10_label>`
+    s_subvector_loop_end           :ref:`sdst<amdgpu_synid10_sdst32_1>`,     :ref:`label<amdgpu_synid10_label>`
+    s_version                                :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_waitcnt_expcnt                         :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_waitcnt_lgkmcnt                        :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_waitcnt_vmcnt                          :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_waitcnt_vscnt                          :ref:`ssrc<amdgpu_synid10_ssrc32_2>`,     :ref:`imm16<amdgpu_synid10_bimm16>`
+
+SOPP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_barrier
+    s_branch                       :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_cdbgsys              :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_cdbgsys_and_user     :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_cdbgsys_or_user      :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_cdbguser             :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_execnz               :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_execz                :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_scc0                 :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_scc1                 :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_vccnz                :ref:`label<amdgpu_synid10_label>`
+    s_cbranch_vccz                 :ref:`label<amdgpu_synid10_label>`
+    s_clause                       :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_code_end
+    s_decperflevel                 :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_denorm_mode                  :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_endpgm
+    s_endpgm_ordered_ps_done
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_inst_prefetch                :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_nop                          :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_round_mode                   :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_sendmsg                      :ref:`msg<amdgpu_synid10_msg>`
+    s_sendmsghalt                  :ref:`msg<amdgpu_synid10_msg>`
+    s_sethalt                      :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_setkill                      :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_setprio                      :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_sleep                        :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_trap                         :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_ttracedata
+    s_ttracedata_imm               :ref:`imm16<amdgpu_synid10_bimm16>`
+    s_waitcnt                      :ref:`waitcnt<amdgpu_synid10_waitcnt>`
+    s_wakeup
+
+VINTRP
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_interp_mov_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`param<amdgpu_synid10_param>`::ref:`b32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_interp_p1_f32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`,      :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_interp_p2_f32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`,      :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`
+
+VOP1
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_bfrev_b32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ceil_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ceil_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ceil_f64                     :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_clrexcp
+    v_cos_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cos_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_cvt_norm_i16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_norm_u16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_exp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_exp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ffbh_i32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ffbh_u32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_ffbl_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_floor_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_floor_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_floor_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_fract_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_fract_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_fract_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_mant_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_log_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_log_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_mov_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_movreld_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_movrels_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_movrelsd_2_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_movrelsd_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_nop
+    v_not_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_pipeflush
+    v_rcp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rcp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rcp_f64                      :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid10_sdst32_2>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_1>`
+    v_rndne_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rndne_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rndne_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_rsq_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rsq_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rsq_f64                      :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_sat_pk_u8_i16                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sin_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sin_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sqrt_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sqrt_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sqrt_f64                     :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+    v_swap_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_swaprel_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_trunc_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_trunc_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_trunc_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
+
+VOP2
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**      **SRC1**      **SRC2**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_add_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_add_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_add_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmaak_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`imm32<amdgpu_synid10_fimm16>`
+    v_fmaak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`imm32<amdgpu_synid10_fimm32>`
+    v_fmac_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmac_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmamk_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`imm32<amdgpu_synid10_fimm16>`,    :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_fmamk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`imm32<amdgpu_synid10_fimm32>`,    :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_ldexp_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mac_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mac_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_madak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`imm32<amdgpu_synid10_fimm32>`
+    v_madmk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`imm32<amdgpu_synid10_fimm32>`,    :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_max_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_pk_fmac_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_sub_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_sub_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_sub_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_co_ci_u32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_subrev_f16                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_nc_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_xnor_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+
+VOP3
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**             **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_add_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_lshl_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_add_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_add_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_add_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_alignbyte_b32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_and_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_and_or_b32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_ashrrev_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_ashrrev_i64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_bfe_i32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+    v_bfe_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_bfi_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_bfm_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ceil_f64_e64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_clrexcp_e64
+    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_f_i64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_f_u64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_t_i64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_t_u64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64                        :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f32_e64                        :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f64_e64                        :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_eq_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_eq_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_f_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_i32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_f_i64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_f_u32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_f_u64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_ge_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_ge_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_gt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_gt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_le_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_le_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_lg_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_lt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_ne_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_ne_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_neq_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_i32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_t_i64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_t_u32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_t_u64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
+    v_cmpx_tru_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`
+    v_cos_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_norm_u16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
+    v_cvt_pknorm_i16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_scale_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`,     :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_div_scale_f64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`,     :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`,       :ref:`src2<amdgpu_synid10_src64_0>`
+    v_exp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_floor_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_floor_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fmac_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmac_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f64_e64    :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1ll_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,           :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`,  :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`                    :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1lv_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,           :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid10_type_dev>`   :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i16<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64             :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_log_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_lshl_or_b32           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`
+    v_lshlrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_lshlrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_lshrrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
+    v_lshrrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_mac_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`i64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`u64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_max3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_max_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_max_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_max_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_max_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_med3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_med3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_min3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_min3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_min_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_min_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_min_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_min_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mov_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_movrels_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_movrelsd_2_b32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_movrelsd_b32_e64      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
+    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b128<amdgpu_synid10_type_dev>`,          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc128_0>`::ref:`b128<amdgpu_synid10_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_hi_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_lo_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_mullit_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_nop_e64
+    v_not_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_or3_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_or_b32_e64            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_pack_b32_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_perm_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_permlane16_b32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`,      :ref:`ssrc2<amdgpu_synid10_ssrc32_3>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_permlanex16_b32       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`,      :ref:`ssrc2<amdgpu_synid10_ssrc32_3>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_pipeflush_e64
+    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f64_e64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32          :ref:`sdst<amdgpu_synid10_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f64_e64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8             :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u16x2<amdgpu_synid10_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_sin_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f64_e64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_sub_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_sub_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_ci_u32_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_u32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_nc_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64        :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_writelane_b32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid10_ssrc32_5>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
+    v_xad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_xnor_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_xor3_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_xor_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+
+VOP3P
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**           **DST**      **SRC0**        **SRC1**     **SRC2**       **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_fma_mix_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_mixhi_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_mixlo_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`fx<amdgpu_synid10_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_fma_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,    :ref:`src2<amdgpu_synid10_src32_2>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mad_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,    :ref:`src2<amdgpu_synid10_src32_2>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mad_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,    :ref:`src2<amdgpu_synid10_src32_2>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_cmp_class_f16                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f32                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f64                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_i64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_u64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_o_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_t_i64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_t_u64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_u_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_class_f16                         :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f32                         :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f64                         :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_eq_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_eq_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_eq_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_f_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_f_i32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_i64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_f_u32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_u64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ge_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ge_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ge_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_gt_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_gt_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_gt_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_le_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_le_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_le_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_lg_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lg_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lg_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_lt_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_lt_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_lt_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ne_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ne_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_neq_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_neq_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_neq_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_nge_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nge_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nge_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_ngt_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ngt_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ngt_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_nle_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nle_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nle_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_nlg_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlg_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlg_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_nlt_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlt_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlt_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_o_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_o_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_o_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_t_i32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_t_i64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_t_u32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_t_u64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_tru_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_tru_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_tru_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+    v_cmpx_u_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_u_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_u_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+
+.. toctree::
+    :hidden:
+
+    gfx10_attr
+    gfx10_bimm16
+    gfx10_bimm32
+    gfx10_fimm16
+    gfx10_fimm32
+    gfx10_hwreg
+    gfx10_label
+    gfx10_msg
+    gfx10_param
+    gfx10_perm_smem
+    gfx10_simm16
+    gfx10_tgt
+    gfx10_uimm16
+    gfx10_vcc_32
+    gfx10_waitcnt
+    gfx10_addr_buf
+    gfx10_addr_ds
+    gfx10_addr_flat
+    gfx10_addr_mimg
+    gfx10_base_smem_addr
+    gfx10_base_smem_buf
+    gfx10_base_smem_scratch
+    gfx10_data_buf_atomic128
+    gfx10_data_buf_atomic32
+    gfx10_data_buf_atomic64
+    gfx10_data_mimg_atomic_cmp
+    gfx10_data_mimg_atomic_reg
+    gfx10_data_mimg_store
+    gfx10_data_mimg_store_d16
+    gfx10_data_smem_atomic128
+    gfx10_data_smem_atomic32
+    gfx10_data_smem_atomic64
+    gfx10_dst_buf_128
+    gfx10_dst_buf_32
+    gfx10_dst_buf_64
+    gfx10_dst_buf_96
+    gfx10_dst_buf_lds
+    gfx10_dst_flat_atomic32
+    gfx10_dst_flat_atomic64
+    gfx10_dst_mimg_gather4
+    gfx10_dst_mimg_regular
+    gfx10_dst_mimg_regular_d16
+    gfx10_offset_buf
+    gfx10_offset_smem_buf
+    gfx10_offset_smem_plain
+    gfx10_rsrc_buf
+    gfx10_rsrc_mimg
+    gfx10_saddr_flat_global
+    gfx10_saddr_flat_scratch
+    gfx10_samp_mimg
+    gfx10_sdata128_0
+    gfx10_sdata32_0
+    gfx10_sdata64_0
+    gfx10_sdst128_0
+    gfx10_sdst256_0
+    gfx10_sdst32_0
+    gfx10_sdst32_1
+    gfx10_sdst32_2
+    gfx10_sdst512_0
+    gfx10_sdst64_0
+    gfx10_sdst64_1
+    gfx10_src32_0
+    gfx10_src32_1
+    gfx10_src32_2
+    gfx10_src32_3
+    gfx10_src64_0
+    gfx10_src_exp
+    gfx10_ssrc32_0
+    gfx10_ssrc32_1
+    gfx10_ssrc32_2
+    gfx10_ssrc32_3
+    gfx10_ssrc32_4
+    gfx10_ssrc32_5
+    gfx10_ssrc64_0
+    gfx10_ssrc64_1
+    gfx10_vaddr_flat_global
+    gfx10_vaddr_flat_scratch
+    gfx10_vdata128_0
+    gfx10_vdata32_0
+    gfx10_vdata64_0
+    gfx10_vdata96_0
+    gfx10_vdst128_0
+    gfx10_vdst32_0
+    gfx10_vdst64_0
+    gfx10_vdst96_0
+    gfx10_vsrc128_0
+    gfx10_vsrc32_0
+    gfx10_vsrc32_1
+    gfx10_vsrc64_0
+    gfx10_wsdst
+    gfx10_wssrc
+    gfx10_mad_type_dev
+    gfx10_mod_dpp_sdwa_abs_neg
+    gfx10_mod_sdwa_sext
+    gfx10_mod_vop3_abs_neg
+    gfx10_opt
+    gfx10_ret
+    gfx10_type_dev
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
index b2671498ee00..1933aff3bb7c 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
@@ -188,7 +188,7 @@ FLAT
 .. parsed-literal::
 
     **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**             **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     flat_atomic_add                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     flat_atomic_add_x2             :ref:`vdst<amdgpu_synid7_dst_flat_atomic64>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     flat_atomic_and                :ref:`vdst<amdgpu_synid7_dst_flat_atomic32>`::ref:`opt<amdgpu_synid7_opt>`,     :ref:`vaddr<amdgpu_synid7_addr_flat>`,    :ref:`vdata<amdgpu_synid7_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -555,22 +555,22 @@ SOPK
     s_addk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
     s_cbranch_i_fork                         :ref:`ssrc<amdgpu_synid7_ssrc64_3>`,     :ref:`label<amdgpu_synid7_label>`
     s_cmovk_i32                    :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
-    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
-    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
-    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
-    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
-    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_1>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
+    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_simm16>`
+    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid7_ssrc32_4>`,     :ref:`imm16<amdgpu_synid7_uimm16>`
     s_getreg_b32                   :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`hwreg<amdgpu_synid7_hwreg>`
     s_movk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
     s_mulk_i32                     :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`imm16<amdgpu_synid7_simm16>`
-    s_setreg_b32                   :ref:`hwreg<amdgpu_synid7_hwreg>`,    :ref:`ssrc<amdgpu_synid7_ssrc32_1>`
+    s_setreg_b32                   :ref:`hwreg<amdgpu_synid7_hwreg>`,    :ref:`ssrc<amdgpu_synid7_ssrc32_4>`
     s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid7_hwreg>`,    :ref:`imm32<amdgpu_synid7_bimm32>`
 
 SOPP
@@ -678,7 +678,7 @@ VOP1
     v_rcp_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
     v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_rcp_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
-    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid7_sdst32_2>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
+    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid7_sdst32_2>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_1>`
     v_rndne_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_rndne_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,     :ref:`src<amdgpu_synid7_src64_0>`
     v_rsq_clamp_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
@@ -704,7 +704,7 @@ VOP2
     v_addc_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
     v_and_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_ashr_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_bfm_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_cndmask_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
@@ -716,9 +716,9 @@ VOP2
     v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_ldexp_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`i32<amdgpu_synid7_type_dev>`
     v_lshl_b32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_lshr_b32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`, :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_mac_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_mac_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_madak_f32                    :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`imm32<amdgpu_synid7_fimm32>`
@@ -740,14 +740,14 @@ VOP2
     v_mul_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_mul_u32_u24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_or_b32                       :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
-    v_readlane_b32                 :ref:`sdst<amdgpu_synid7_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid7_vsrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+    v_readlane_b32                 :ref:`sdst<amdgpu_synid7_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid7_vsrc32_1>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
     v_sub_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_sub_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
     v_subb_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
-    v_subbrev_u32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
-    v_subrev_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
-    v_subrev_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
-    v_writelane_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid7_ssrc32_0>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_4>`
+    v_subbrev_u32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_2>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`,    :ref:`vcc<amdgpu_synid7_vcc_64>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_2>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_subrev_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_2>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
+    v_writelane_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid7_ssrc32_6>`,    :ref:`ssrc1<amdgpu_synid7_ssrc32_5>`
     v_xor_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,               :ref:`src0<amdgpu_synid7_src32_0>`,     :ref:`vsrc1<amdgpu_synid7_vsrc32_0>`
 
 VOP3
@@ -757,369 +757,369 @@ VOP3
 
     **INSTRUCTION**                    **DST0**       **DST1**      **SRC0**        **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_addc_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
-    v_alignbit_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_alignbyte_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_and_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_ashr_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_ashr_i64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
-    v_bcnt_u32_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_bfe_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_bfe_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_bfi_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_bfm_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_addc_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_ashr_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_ashr_i64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_4>`
+    v_bcnt_u32_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_bfm_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_eq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_f_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_ge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_gt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_le_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_lg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_lt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_neq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_nge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_ngt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_nle_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_nlg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_nlt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_o_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_tru_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmps_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmps_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmps_u_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_eq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_eq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_eq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_f_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_f_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_f_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_ge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_ge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_gt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_gt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_gt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_le_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_le_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_le_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_lg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_lg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_lt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_lt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_lt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_neq_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_neq_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_neq_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_nge_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nge_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_nge_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_ngt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_ngt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_ngt_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_nle_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nle_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_nle_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_nlg_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlg_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_nlg_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_nlt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_nlt_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_nlt_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_o_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_o_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_o_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_tru_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_tru_f32_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_tru_f64_e64            :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpsx_u_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpsx_u_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpsx_u_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`
-    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
     v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid7_sdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
-    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_5>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
     v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_cvt_pk_u16_u32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_cvt_pkaccum_u8_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_cvt_pknorm_i16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_pknorm_u16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_pkrtz_f16_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
-    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_cvt_pk_u16_u32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_cvt_pkaccum_u8_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_cvt_pknorm_i16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_pknorm_u16_f32_e64       :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_pkrtz_f16_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`
     v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_div_fixup_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
     v_div_scale_f64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`vcc<amdgpu_synid7_vcc_64>`,      :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src64_1>`,       :ref:`src2<amdgpu_synid7_src64_1>`
-    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_floor_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
     v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`
-    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
     v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_log_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshl_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
-    v_lshr_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshr_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mac_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`::ref:`i32<amdgpu_synid7_type_dev>`
-    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
-    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
-    v_max3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_max3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_max_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_log_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshl_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_4>`
+    v_lshr_b32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshr_b64                     :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`,       :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`::ref:`i32<amdgpu_synid7_type_dev>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`i64<amdgpu_synid7_type_dev>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src64_1>`::ref:`u64<amdgpu_synid7_type_dev>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_max_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mbcnt_hi_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mbcnt_lo_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_med3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_med3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_min3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_min3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_min_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_max_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mbcnt_hi_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mbcnt_lo_u32_b32_e64         :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_min_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_movreld_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_min_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_movreld_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
     v_movrels_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
     v_movrelsd_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
-    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
-    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`,           :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
-    v_msad_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`
-    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid7_vdst128_0>`::ref:`b128<amdgpu_synid7_type_dev>`,           :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`vsrc2<amdgpu_synid7_vsrc128_0>`::ref:`b128<amdgpu_synid7_type_dev>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64                      :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_mullit_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_i32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_mullit_f32                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src2<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_nop_e64
-    v_not_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`
-    v_or_b32_e64                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_1>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
-    v_rcp_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid7_vdst64_0>`::ref:`b64<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`,   :ref:`src1<amdgpu_synid7_src32_6>`::ref:`b32<amdgpu_synid7_type_dev>`,   :ref:`src2<amdgpu_synid7_src64_2>`::ref:`b64<amdgpu_synid7_type_dev>`
+    v_rcp_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_clamp_f64_e64            :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_clamp_f32_e64            :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_clamp_f64_e64            :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_sad_u16                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_sad_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`src2<amdgpu_synid7_src32_2>`
-    v_sad_u8                       :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`
-    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u16x2<amdgpu_synid7_type_dev>`, :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`src2<amdgpu_synid7_src32_4>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid7_vdst32_0>`::ref:`u32<amdgpu_synid7_type_dev>`,            :ref:`src0<amdgpu_synid7_src32_1>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src1<amdgpu_synid7_src32_6>`::ref:`u8x4<amdgpu_synid7_type_dev>`,  :ref:`src2<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_subb_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
-    v_subbrev_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
-    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_i32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
-    v_trig_preop_f64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_2>`::ref:`u32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_2>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_subb_u32_e64                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_subbrev_u32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_4>`,       :ref:`src1<amdgpu_synid7_src32_4>`,       :ref:`ssrc2<amdgpu_synid7_ssrc64_1>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_i32_e64               :ref:`vdst<amdgpu_synid7_vdst32_0>`,      :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`src0<amdgpu_synid7_src32_4>`,       :ref:`src1<amdgpu_synid7_src32_4>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src0<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`u32<amdgpu_synid7_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64                :ref:`vdst<amdgpu_synid7_vdst64_0>`,                :ref:`src<amdgpu_synid7_src64_1>`::ref:`m<amdgpu_synid7_mod>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_2>`,       :ref:`src1<amdgpu_synid7_src32_2>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
 
 VOPC
 -----------------------
@@ -1380,6 +1380,9 @@ VOPC
     gfx7_src32_1
     gfx7_src32_2
     gfx7_src32_3
+    gfx7_src32_4
+    gfx7_src32_5
+    gfx7_src32_6
     gfx7_src64_0
     gfx7_src64_1
     gfx7_src64_2
@@ -1389,6 +1392,8 @@ VOPC
     gfx7_ssrc32_2
     gfx7_ssrc32_3
     gfx7_ssrc32_4
+    gfx7_ssrc32_5
+    gfx7_ssrc32_6
     gfx7_ssrc64_0
     gfx7_ssrc64_1
     gfx7_ssrc64_2
@@ -1404,6 +1409,7 @@ VOPC
     gfx7_vdst96_0
     gfx7_vsrc128_0
     gfx7_vsrc32_0
+    gfx7_vsrc32_1
     gfx7_vsrc64_0
     gfx7_mod
     gfx7_opt
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
index a6dbc9be68f0..9c762aa0f838 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
@@ -193,7 +193,7 @@ FLAT
 .. parsed-literal::
 
     **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**             **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     flat_atomic_add                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     flat_atomic_add_x2             :ref:`vdst<amdgpu_synid8_dst_flat_atomic64>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata64_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     flat_atomic_and                :ref:`vdst<amdgpu_synid8_dst_flat_atomic32>`::ref:`opt<amdgpu_synid8_opt>`,     :ref:`vaddr<amdgpu_synid8_addr_flat>`,    :ref:`vdata<amdgpu_synid8_vdata32_0>`            :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -405,7 +405,7 @@ SMEM
 .. parsed-literal::
 
     **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     s_atc_probe                              :ref:`imm3<amdgpu_synid8_perm_smem>`,     :ref:`sbase<amdgpu_synid8_base_smem_addr>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`
     s_atc_probe_buffer                       :ref:`imm3<amdgpu_synid8_perm_smem>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`
     s_buffer_load_dword            :ref:`sdst<amdgpu_synid8_sdst32_0>`,     :ref:`sbase<amdgpu_synid8_base_smem_buf>`,    :ref:`soffset<amdgpu_synid8_offset_smem_load>`                  :ref:`glc<amdgpu_synid_glc>`
@@ -805,7 +805,7 @@ VOP1
     v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
     v_rcp_iflag_f32_dpp            :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_rcp_iflag_f32_sdwa           :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid8_sdst32_2>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
+    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid8_sdst32_2>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_1>`
     v_rndne_f16                    :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
     v_rndne_f16_dpp                :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_rndne_f16_sdwa               :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -866,10 +866,10 @@ VOP2
     v_and_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_and_b32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_and_b32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_ashrrev_i16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_ashrrev_i32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cndmask_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
@@ -878,16 +878,16 @@ VOP2
     v_ldexp_f16           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`
     v_ldexp_f16_dpp       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ldexp_f16_sdwa      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`i16<amdgpu_synid8_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshlrev_b16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshlrev_b32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshrrev_b16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshrrev_b32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mac_f16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -978,19 +978,19 @@ VOP2
     v_subb_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
     v_subb_u32_dpp        :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subb_u32_sdwa       :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_u32         :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_subbrev_u32         :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
     v_subbrev_u32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subbrev_u32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_f16_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_f32_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_u16_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32          :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u32          :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_u32_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_xor_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -1004,290 +1004,290 @@ VOP3
 
     **INSTRUCTION**             **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_add_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_addc_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
-    v_alignbit_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_alignbyte_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_and_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_ashrrev_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_ashrrev_i64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_bfe_i32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_bfe_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_bfi_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_bfm_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_add_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_addc_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_alignbyte_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_and_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_ashrrev_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_ashrrev_i64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_bfe_i32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_bfe_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_bfi_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_bfm_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_eq_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_eq_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_eq_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_f_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_f_i64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_f_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_f_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_f_u64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ge_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_ge_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_ge_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_gt_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_gt_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_gt_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_le_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_le_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_le_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lg_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lt_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_lt_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_lt_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_ne_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_ne_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_neq_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nge_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ngt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nle_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlg_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_o_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_t_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_t_i64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_t_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmp_t_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmp_t_u64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_tru_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_u_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_class_f16_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_class_f32_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_class_f64_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_eq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f32_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f64_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_eq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_eq_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_eq_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_eq_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_eq_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_eq_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_eq_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_eq_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_eq_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_eq_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_f_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_f_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_f_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_f_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_f_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_f_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_f_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_f_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_f_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_f_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ge_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_ge_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ge_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_ge_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ge_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_ge_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ge_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ge_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_ge_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_gt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_gt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_gt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_gt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_gt_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_gt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_gt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_gt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_gt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_gt_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_le_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_le_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_le_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_le_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_le_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_le_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_le_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_le_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_le_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_le_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_lg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lg_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_lt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_lt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_lt_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_lt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_lt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_lt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_lt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_lt_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ne_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_ne_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ne_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_ne_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ne_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_ne_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_ne_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ne_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_ne_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_neq_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_neq_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_neq_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nge_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ngt_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nle_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlg_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlt_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_o_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_t_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_t_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_t_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_t_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_t_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cmpx_t_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_cmpx_t_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_t_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_cmpx_t_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_tru_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_tru_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_tru_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_u_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
-    v_cos_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cos_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_cos_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_cvt_i32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_cvt_pkaccum_u8_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_pkrtz_f16_f32     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pkaccum_u8_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_cvt_u32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_div_fixup_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
+    v_div_scale_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
     v_div_scale_f64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`
-    v_exp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_exp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_floor_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_floor_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_floor_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_frexp_mant_f64_e64    :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_mov_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`param<amdgpu_synid8_param>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1295,116 +1295,116 @@ VOP3
     v_interp_p1lv_f16       :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`f32<amdgpu_synid8_type_dev>`,           :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid8_type_dev>`   :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p2_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
     v_interp_p2_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i16<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64             :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_log_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_log_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_lshlrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_lshrrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`
-    v_lshrrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_mac_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mac_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`::ref:`i32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i64_i32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u64_u32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_max3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_max_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_max_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i16<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64             :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_log_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_lshlrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_lshrrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
+    v_lshrrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_mac_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_max3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_max_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_max_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_max_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_max_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_med3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_med3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_min3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_min3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_min_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_min_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_max_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_max_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_max_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_med3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_med3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_min3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_min3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_min_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_min_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_min_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_min_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mov_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_mov_fed_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
+    v_min_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_min_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_min_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_min_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mov_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_mov_fed_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
     v_movrels_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
     v_movrelsd_b32_e64      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
-    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`,          :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
-    v_msad_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`,          :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_hi_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_lo_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_mul_hi_i32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_hi_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_lo_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
     v_nop_e64
-    v_not_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`
-    v_or_b32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_perm_b32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`
-    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_1>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_or_b32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_perm_b32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_readlane_b32          :ref:`sdst<amdgpu_synid8_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
-    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32          :ref:`sdst<amdgpu_synid8_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
+    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8             :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`,  :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`src2<amdgpu_synid8_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u8                :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8             :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16x2<amdgpu_synid8_type_dev>`,  :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_sub_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_subb_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
-    v_subbrev_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
-    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_subrev_u32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
-    v_trig_preop_f64        :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_sub_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subb_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subbrev_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_subrev_u32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64        :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_writelane_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid8_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
-    v_xor_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`src1<amdgpu_synid8_src32_1>`
+    v_xor_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
 
 VOPC
 -----------------------
@@ -1814,6 +1814,8 @@ VOPC
     gfx8_sdst64_1
     gfx8_src32_0
     gfx8_src32_1
+    gfx8_src32_2
+    gfx8_src32_3
     gfx8_src64_0
     gfx8_src64_1
     gfx8_src_exp
@@ -1837,6 +1839,7 @@ VOPC
     gfx8_vdst96_0
     gfx8_vsrc128_0
     gfx8_vsrc32_0
+    gfx8_vsrc32_1
     gfx8_vsrc64_0
     gfx8_mod_dpp_sdwa_abs_neg
     gfx8_mod_sdwa_sext
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
index 9dd3b9de2602..3ffb9fd5c8db 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
@@ -501,7 +501,7 @@ SMEM
 .. parsed-literal::
 
     **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**           **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     s_atc_probe                              :ref:`imm3<amdgpu_synid9_perm_smem>`,            :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
     s_atc_probe_buffer                       :ref:`imm3<amdgpu_synid9_perm_smem>`,            :ref:`sbase<amdgpu_synid9_base_smem_buf>`,    :ref:`soffset<amdgpu_synid9_offset_smem_buf>`
     s_atomic_add                             :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`,       :ref:`sbase<amdgpu_synid9_base_smem_addr>`,    :ref:`soffset<amdgpu_synid9_offset_smem_plain>`        :ref:`glc<amdgpu_synid_glc>`
@@ -980,7 +980,7 @@ VOP1
     v_rcp_iflag_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_rcp_iflag_f32_dpp             :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_rcp_iflag_f32_sdwa            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_readfirstlane_b32             :ref:`sdst<amdgpu_synid9_sdst32_2>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`
+    v_readfirstlane_b32             :ref:`sdst<amdgpu_synid9_sdst32_2>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_1>`
     v_rndne_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_rndne_f16_dpp                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_rndne_f16_sdwa                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -1051,30 +1051,30 @@ VOP2
     v_and_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_and_b32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_and_b32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_ashrrev_i16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_ashrrev_i32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cndmask_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_cndmask_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cndmask_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_ldexp_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`
     v_ldexp_f16_dpp       :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ldexp_f16_sdwa      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`i16<amdgpu_synid9_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshlrev_b16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshlrev_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshrrev_b16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshrrev_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mac_f16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_mac_f16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mac_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
@@ -1164,24 +1164,24 @@ VOP2
     v_subb_co_u32         :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_subb_co_u32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subb_co_u32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_co_u32      :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_subbrev_co_u32      :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_subbrev_co_u32_dpp  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_co_u32       :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_co_u32       :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_co_u32_dpp   :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_co_u32_sdwa  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_co_u32_sdwa  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_f16_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_f32_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_u16_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_u32_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_xor_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_xor_b32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_xor_b32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1193,302 +1193,302 @@ VOP3
 
     **INSTRUCTION**                    **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_add_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_add_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_add_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_add_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_add_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_addc_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
-    v_alignbit_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_alignbyte_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_and_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_and_or_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_bfe_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_bfe_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_bfi_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_bfm_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_add_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_add_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_addc_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_and_or_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
-    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_norm_i16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_norm_u16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_cvt_pknorm_i16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_pknorm_u16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_norm_u16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pknorm_i16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
     v_div_scale_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`
-    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_floor_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_floor_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_floor_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
     v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_mov_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1497,138 +1497,138 @@ VOP3
     v_interp_p2_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
     v_interp_p2_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p2_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i16<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_log_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_log_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`
-    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`
-    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_u16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_max3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_max_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_max_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i16<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_log_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`
+    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
+    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_u16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_max3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_max_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_max_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_max_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_max_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_med3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_med3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_med3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_min3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_min3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_min3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_min_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_min_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_max_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_med3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_med3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_min3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_min3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_min_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_min_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_min_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_min_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`,          :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
-    v_msad_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_min_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`,          :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
     v_nop_e64
-    v_not_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_or3_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_or_b32_e64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_perm_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_or3_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_perm_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_readlane_b32                 :ref:`sdst<amdgpu_synid9_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
-    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_readlane_b32                 :ref:`sdst<amdgpu_synid9_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
+    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`,  :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u8                       :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sat_pk_u8_i16_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`
-    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16x2<amdgpu_synid9_type_dev>`,  :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
+    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_subb_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
-    v_subbrev_co_u32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
-    v_subrev_co_u32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
-    v_trig_preop_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subb_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subbrev_co_u32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_u32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_writelane_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid9_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
-    v_xad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`,       :ref:`src2<amdgpu_synid9_src32_1>`
-    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_1>`,        :ref:`src1<amdgpu_synid9_src32_1>`
+    v_xad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
 
 VOP3P
 -----------------------
@@ -1637,28 +1637,28 @@ VOP3P
 
     **INSTRUCTION**           **DST**      **SRC0**        **SRC1**     **SRC2**       **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_mad_mix_f32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_mixhi_f16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_mixlo_f16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_1>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_fma_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,    :ref:`src2<amdgpu_synid9_src32_1>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mad_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,    :ref:`src2<amdgpu_synid9_src32_1>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mad_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`,    :ref:`src2<amdgpu_synid9_src32_1>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_max_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_min_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mul_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_sub_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_sub_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`src1<amdgpu_synid9_src32_1>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mix_f32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixhi_f16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_mixlo_f16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`::ref:`fx<amdgpu_synid9_mad_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`fx<amdgpu_synid9_mad_type_dev>`    :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_fma_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mad_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mad_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
 
 VOPC
 -----------------------
@@ -2067,6 +2067,8 @@ VOPC
     gfx9_sdst64_1
     gfx9_src32_0
     gfx9_src32_1
+    gfx9_src32_2
+    gfx9_src32_3
     gfx9_src64_0
     gfx9_src64_1
     gfx9_src_exp
@@ -2092,6 +2094,7 @@ VOPC
     gfx9_vdst96_0
     gfx9_vsrc128_0
     gfx9_vsrc32_0
+    gfx9_vsrc32_1
     gfx9_vsrc64_0
     gfx9_mad_type_dev
     gfx9_mod_dpp_sdwa_abs_neg
diff --git a/llvm/docs/AMDGPU/gfx10_addr_buf.rst b/llvm/docs/AMDGPU/gfx10_addr_buf.rst
new file mode 100644
index 000000000000..bd57e9e2fcdb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_buf.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_addr_buf:
+
+vaddr
+===========================
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_ds.rst b/llvm/docs/AMDGPU/gfx10_addr_ds.rst
new file mode 100644
index 000000000000..b31862f2ec75
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_ds.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_addr_ds:
+
+vaddr
+===========================
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_flat.rst b/llvm/docs/AMDGPU/gfx10_addr_flat.rst
new file mode 100644
index 000000000000..cd780ca0cbe1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_flat.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_addr_flat:
+
+vaddr
+===========================
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
new file mode 100644
index 000000000000..882fd8c9f61a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
@@ -0,0 +1,23 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_addr_mimg:
+
+vaddr
+===========================
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_vcc_lo>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_attr.rst b/llvm/docs/AMDGPU/gfx10_attr.rst
new file mode 100644
index 000000000000..f32f085f35ba
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_attr.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_attr:
+
+attr
+===========================
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+    v_interp_p1_f32 v1, v0, attr0.x
+    v_interp_p1_f32 v1, v0, attr32.w
+
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst b/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst
new file mode 100644
index 000000000000..9d5211432f9f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_addr.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_base_smem_addr:
+
+sbase
+===========================
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst
new file mode 100644
index 000000000000..00e987d7bb46
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_base_smem_buf:
+
+sbase
+===========================
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst b/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst
new file mode 100644
index 000000000000..2b7e8b4cd4b1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_base_smem_scratch.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_base_smem_scratch:
+
+sbase
+===========================
+
+This operand is ignored by H/W and :ref:`flat_scratch<amdgpu_synid_flat_scratch>` is supplied instead.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_bimm16.rst b/llvm/docs/AMDGPU/gfx10_bimm16.rst
new file mode 100644
index 000000000000..00e9b71b92e7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_bimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_bimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_bimm32.rst b/llvm/docs/AMDGPU/gfx10_bimm32.rst
new file mode 100644
index 000000000000..c4b87df907f7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_bimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_bimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst
new file mode 100644
index 000000000000..3ca9fb9c3eaf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic128:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst
new file mode 100644
index 000000000000..a8e6d9fd61d8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic32:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst b/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst
new file mode 100644
index 000000000000..3840cd5d92e9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_buf_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_buf_atomic64:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
new file mode 100644
index 000000000000..bd257cf570b8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
@@ -0,0 +1,27 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_mimg_atomic_cmp:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
new file mode 100644
index 000000000000..930dab31321d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
@@ -0,0 +1,26 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_mimg_atomic_reg:
+
+vdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+  Note. The surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst
new file mode 100644
index 000000000000..156c1b0180e5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_store.rst
@@ -0,0 +1,18 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_mimg_store:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst b/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst
new file mode 100644
index 000000000000..142b3060422e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_mimg_store_d16.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_mimg_store_d16:
+
+vdata
+===========================
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst
new file mode 100644
index 000000000000..c59c4888fabd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic128.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic128:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst
new file mode 100644
index 000000000000..5e8f7ca30204
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic32.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic32:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
new file mode 100644
index 000000000000..a8d52492f9f0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_data_smem_atomic64:
+
+sdata
+===========================
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst
new file mode 100644
index 000000000000..56cfc2f10180
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_128.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_buf_128:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst
new file mode 100644
index 000000000000..a1f1dc99ffb8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_buf_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst
new file mode 100644
index 000000000000..ebd3c7e3f173
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_64.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_buf_64:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst
new file mode 100644
index 000000000000..13a7e2bfc966
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_96.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_buf_96:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst b/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst
new file mode 100644
index 000000000000..ec83bf56931e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_buf_lds.rst
@@ -0,0 +1,21 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_buf_lds:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+    Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst
new file mode 100644
index 000000000000..e8d94b855953
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic32.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_flat_atomic32:
+
+vdst
+===========================
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst
new file mode 100644
index 000000000000..19d9b11ba8c9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_flat_atomic64.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_flat_atomic64:
+
+vdst
+===========================
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst
new file mode 100644
index 000000000000..90b859353880
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_gather4.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_mimg_gather4:
+
+vdst
+===========================
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+
+:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst
new file mode 100644
index 000000000000..d3379356ee72
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_mimg_regular:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
new file mode 100644
index 000000000000..9217574c9c42
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_dst_mimg_regular_d16:
+
+vdst
+===========================
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_fimm16.rst b/llvm/docs/AMDGPU/gfx10_fimm16.rst
new file mode 100644
index 000000000000..c4d85be860d6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_fimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_fimm16:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The number is converted to *f16* as described :ref:`here<amdgpu_synid_lit_conv>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_fimm32.rst b/llvm/docs/AMDGPU/gfx10_fimm32.rst
new file mode 100644
index 000000000000..7ff84cc051b6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_fimm32.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_fimm32:
+
+imm32
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or a :ref:`floating-point_number<amdgpu_synid_floating-point_number>`. The value is converted to *f32* as described :ref:`here<amdgpu_synid_lit_conv>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst
new file mode 100644
index 000000000000..64d441bc72f5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst
@@ -0,0 +1,69 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_hwreg:
+
+hwreg
+===========================
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ============ ===================================
+    Bits         Description
+    ============ ===================================
+    5:0          Register *id*.
+    10:6         First bit *offset* (0..31).
+    15:11        *Size* in bits (1..32).
+    ============ ===================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
+
+    ==================================== ============================================================================
+    Syntax                               Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES Memory aperture.
+    HW_REG_TBA_LO       tba_lo register.
+    HW_REG_TBA_HI       tba_hi register.
+    HW_REG_TMA_LO       tma_lo register.
+    HW_REG_TMA_HI       tma_hi register.
+    HW_REG_FLAT_SCR_LO  flat_scratch_lo register.
+    HW_REG_FLAT_SCR_HI  flat_scratch_hi register.
+    HW_REG_XNACK_MASK   xnack_mask register.
+    HW_REG_POPS_PACKER  pops_packer register.
+    =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+    s_getreg_b32 s2, 0x6
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
+
diff --git a/llvm/docs/AMDGPU/gfx10_label.rst b/llvm/docs/AMDGPU/gfx10_label.rst
new file mode 100644
index 000000000000..288c6c023a5c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_label.rst
@@ -0,0 +1,30 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_label:
+
+label
+===========================
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>`. The number is truncated to 16 bits.
+* An :ref:`absolute_expression<amdgpu_synid_absolute_expression>` which must start with an :ref:`integer_number<amdgpu_synid_integer_number>`. The value of the expression is truncated to 16 bits.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label). The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+  offset = 30
+  s_branch loop_end
+  s_branch 2 + offset
+  s_branch 32
+  loop_end:
+
diff --git a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
new file mode 100644
index 000000000000..bbf04e7ba5e5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_mad_type_dev:
+
+fx
+===========================
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
new file mode 100644
index 000000000000..dfa8c07293fd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_mod_dpp_sdwa_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
new file mode 100644
index 000000000000..b7e0e3e0f927
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_mod_sdwa_sext:
+
+m
+===========================
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
new file mode 100644
index 000000000000..9f6b6abdcb36
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_mod_vop3_abs_neg:
+
+m
+===========================
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
+
diff --git a/llvm/docs/AMDGPU/gfx10_msg.rst b/llvm/docs/AMDGPU/gfx10_msg.rst
new file mode 100644
index 000000000000..d56daa5c240d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_msg.rst
@@ -0,0 +1,73 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_msg:
+
+msg
+===========================
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          Message *type*.
+    6:4          Optional *operation*.
+    9:7          Optional *parameters*.
+    15:10        Unused.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below:
+
+    ======================================== ========================================================================
+    Syntax                                   Description
+    ======================================== ========================================================================
+    sendmsg(<*type*>)                        A message identified by its *type*.
+    sendmsg(<*type*>, <*op*>)                A message identified by its *type* and *operation*.
+    sendmsg(<*type*>, <*op*>, <*stream*>)    A message identified by its *type* and *operation* with a stream *id*.
+    ======================================== ========================================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Message *id*, operation *id* and stream *id* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
+
+Each message type supports specific operations:
+
+    ================= ========== ============================== ============ ==========
+    Message name      Message Id Supported Operations           Operation Id Stream Id
+    ================= ========== ============================== ============ ==========
+    MSG_INTERRUPT     1          \-                             \-           \-
+    MSG_GS            2          GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_DONE       3          GS_OP_NOP                      0            \-
+    \                            GS_OP_CUT                      1            Optional
+    \                            GS_OP_EMIT                     2            Optional
+    \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_ALLOC_REQ  9          \-                             \-           \-
+    MSG_SYSMSG        15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
+    \                            SYSMSG_OP_REG_RD               2            \-
+    \                            SYSMSG_OP_HOST_TRAP_ACK        3            \-
+    \                            SYSMSG_OP_TTRACE_PC            4            \-
+    ================= ========== ============================== ============ ==========
+
+Examples:
+
+.. parsed-literal::
+
+    s_sendmsg 0x12
+    s_sendmsg sendmsg(MSG_INTERRUPT)
+    s_sendmsg sendmsg(2, GS_OP_CUT)
+    s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+    s_sendmsg sendmsg(MSG_GS, 2)
+    s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+    s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+
diff --git a/llvm/docs/AMDGPU/gfx10_offset_buf.rst b/llvm/docs/AMDGPU/gfx10_offset_buf.rst
new file mode 100644
index 000000000000..99598fdd1516
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_offset_buf:
+
+soffset
+===========================
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
new file mode 100644
index 000000000000..b382317fa5a9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_offset_smem_buf:
+
+soffset
+===========================
+
+An unsigned byte offset added to the base address to get memory address.
+
+.. WARNING:: Assembler currently supports 20-bit offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`uimm21<amdgpu_synid_uimm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm21<amdgpu_synid_uimm21>`
diff --git a/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
new file mode 100644
index 000000000000..09ef0227ae11
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_offset_smem_plain:
+
+soffset
+===========================
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx10_opt.rst b/llvm/docs/AMDGPU/gfx10_opt.rst
new file mode 100644
index 000000000000..d7dbba331801
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_opt.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_opt:
+
+opt
+===========================
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
diff --git a/llvm/docs/AMDGPU/gfx10_param.rst b/llvm/docs/AMDGPU/gfx10_param.rst
new file mode 100644
index 000000000000..afa91e345701
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_param.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_param:
+
+param
+===========================
+
+Interpolation parameter to read:
+
+    ============ ===================================
+    Syntax       Description
+    ============ ===================================
+    p0           Parameter *P0*.
+    p10          Parameter *P10*.
+    p20          Parameter *P20*.
+    ============ ===================================
+
diff --git a/llvm/docs/AMDGPU/gfx10_perm_smem.rst b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
new file mode 100644
index 000000000000..879b33de1dff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
@@ -0,0 +1,24 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_perm_smem:
+
+imm3
+===========================
+
+A bit mask which indicates request permissions.
+
+This operand must be specified as an :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 7 bits, but only 3 low bits are significant.
+
+    ============ ==============================
+    Bit Number   Description
+    ============ ==============================
+    0            Request *read* permission.
+    1            Request *write* permission.
+    2            Request *execute* permission.
+    ============ ==============================
+
diff --git a/llvm/docs/AMDGPU/gfx10_ret.rst b/llvm/docs/AMDGPU/gfx10_ret.rst
new file mode 100644
index 000000000000..2003437c2079
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ret.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ret:
+
+dst
+===========================
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
+
diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst b/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst
new file mode 100644
index 000000000000..a3f454b40191
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_rsrc_buf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_rsrc_buf:
+
+srsrc
+===========================
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst b/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst
new file mode 100644
index 000000000000..af830b0a2c8d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_rsrc_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_rsrc_mimg:
+
+srsrc
+===========================
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst
new file mode 100644
index 000000000000..2362d0c020ef
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_saddr_flat_global.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_saddr_flat_global:
+
+saddr
+===========================
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst
new file mode 100644
index 000000000000..8fea5d304288
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_saddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_saddr_flat_scratch:
+
+saddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_samp_mimg.rst b/llvm/docs/AMDGPU/gfx10_samp_mimg.rst
new file mode 100644
index 000000000000..5f2aed088f11
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_samp_mimg.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_samp_mimg:
+
+ssamp
+===========================
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata128_0.rst b/llvm/docs/AMDGPU/gfx10_sdata128_0.rst
new file mode 100644
index 000000000000..19d6e5bc2eef
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdata128_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata32_0.rst b/llvm/docs/AMDGPU/gfx10_sdata32_0.rst
new file mode 100644
index 000000000000..10e10caf626b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdata32_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
new file mode 100644
index 000000000000..a47fb083a834
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdata64_0:
+
+sdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst128_0.rst b/llvm/docs/AMDGPU/gfx10_sdst128_0.rst
new file mode 100644
index 000000000000..e1bfc693c0ea
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst128_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst256_0.rst b/llvm/docs/AMDGPU/gfx10_sdst256_0.rst
new file mode 100644
index 000000000000..c352bffeebb7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst256_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst256_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_0.rst b/llvm/docs/AMDGPU/gfx10_sdst32_0.rst
new file mode 100644
index 000000000000..1000d83ffc2e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst32_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_1.rst b/llvm/docs/AMDGPU/gfx10_sdst32_1.rst
new file mode 100644
index 000000000000..ddfb348c3de8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst32_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst32_2.rst b/llvm/docs/AMDGPU/gfx10_sdst32_2.rst
new file mode 100644
index 000000000000..41a078ba4238
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst32_2:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst512_0.rst b/llvm/docs/AMDGPU/gfx10_sdst512_0.rst
new file mode 100644
index 000000000000..f72a2d5e0280
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst512_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst512_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
new file mode 100644
index 000000000000..a70da808e0d8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst64_0:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
new file mode 100644
index 000000000000..483a4e3f1a79
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_sdst64_1:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_simm16.rst b/llvm/docs/AMDGPU/gfx10_simm16.rst
new file mode 100644
index 000000000000..eb1d171e5290
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_simm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_simm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then sign-extended to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_src32_0.rst b/llvm/docs/AMDGPU/gfx10_src32_0.rst
new file mode 100644
index 000000000000..f4ae944c9601
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_1.rst b/llvm/docs/AMDGPU/gfx10_src32_1.rst
new file mode 100644
index 000000000000..a1be1e1c3396
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_1:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_2.rst b/llvm/docs/AMDGPU/gfx10_src32_2.rst
new file mode 100644
index 000000000000..9b8fd6f5054b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_3.rst b/llvm/docs/AMDGPU/gfx10_src32_3.rst
new file mode 100644
index 000000000000..b9348220136d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_src64_0.rst b/llvm/docs/AMDGPU/gfx10_src64_0.rst
new file mode 100644
index 000000000000..f88ccf2a68c9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src64_0:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src_exp.rst b/llvm/docs/AMDGPU/gfx10_src_exp.rst
new file mode 100644
index 000000000000..4dd387a3aed4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src_exp.rst
@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src_exp:
+
+vsrc
+===========================
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. parsed-literal::
+
+  exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst
new file mode 100644
index 000000000000..e444898cdc15
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst
new file mode 100644
index 000000000000..4fdbe1c099eb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst
new file mode 100644
index 000000000000..1b46e77a43c6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_2:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst
new file mode 100644
index 000000000000..ec6b1152dfa1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_3:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst
new file mode 100644
index 000000000000..bba8d5aeaa18
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_4:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst
new file mode 100644
index 000000000000..a0b1bbf0463f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc32_5:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
new file mode 100644
index 000000000000..774682627a7a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc64_0:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
new file mode 100644
index 000000000000..bd13d35b2848
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_ssrc64_1:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst
new file mode 100644
index 000000000000..b6569c73b9eb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_tgt.rst
@@ -0,0 +1,25 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_tgt:
+
+tgt
+===========================
+
+An export target:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    pos{0..4}      Copy vertex position 0..4.
+    param{0..31}   Copy vertex parameter 0..31.
+    mrt{0..7}      Copy pixel color to the MRTs 0..7.
+    mrtz           Copy pixel depth (Z) data.
+    prim           Copy primitive (connectivity) data.
+    null           Copy nothing.
+    ============== ===================================
+
diff --git a/llvm/docs/AMDGPU/gfx10_type_dev.rst b/llvm/docs/AMDGPU/gfx10_type_dev.rst
new file mode 100644
index 000000000000..8978fbeb4a0d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_type_dev.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_type_dev:
+
+Type deviation
+===========================
+
+*Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
+
diff --git a/llvm/docs/AMDGPU/gfx10_uimm16.rst b/llvm/docs/AMDGPU/gfx10_uimm16.rst
new file mode 100644
index 000000000000..f4bfe8c924ba
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_uimm16.rst
@@ -0,0 +1,14 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_uimm16:
+
+imm16
+===========================
+
+An :ref:`integer_number<amdgpu_synid_integer_number>`. The value is truncated to 16 bits and then zero-extended to 32 bits.
+
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
new file mode 100644
index 000000000000..0d44a1a0caa8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
@@ -0,0 +1,22 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vaddr_flat_global:
+
+vaddr
+===========================
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid10_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid10_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid10_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
+
+.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
new file mode 100644
index 000000000000..cc6d1af64eed
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
@@ -0,0 +1,19 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vaddr_flat_scratch:
+
+vaddr
+===========================
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+Either this operand or :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>` must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx10_vcc_32.rst b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
new file mode 100644
index 000000000000..1e730073c2f0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vcc_32:
+
+vcc
+===========================
+
+Vector condition code. This operand depends on wavefront size:
+
+* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
+* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
+
diff --git a/llvm/docs/AMDGPU/gfx10_vdata128_0.rst b/llvm/docs/AMDGPU/gfx10_vdata128_0.rst
new file mode 100644
index 000000000000..0e25049065ee
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdata128_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata32_0.rst b/llvm/docs/AMDGPU/gfx10_vdata32_0.rst
new file mode 100644
index 000000000000..e2ddcee736b7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdata32_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata64_0.rst b/llvm/docs/AMDGPU/gfx10_vdata64_0.rst
new file mode 100644
index 000000000000..4552a3998fe9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdata64_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdata96_0.rst b/llvm/docs/AMDGPU/gfx10_vdata96_0.rst
new file mode 100644
index 000000000000..084825a6331b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdata96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdata96_0:
+
+vdata
+===========================
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst128_0.rst b/llvm/docs/AMDGPU/gfx10_vdst128_0.rst
new file mode 100644
index 000000000000..a0a786c3b693
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdst128_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst32_0.rst b/llvm/docs/AMDGPU/gfx10_vdst32_0.rst
new file mode 100644
index 000000000000..d04548ec1eae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdst32_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst64_0.rst b/llvm/docs/AMDGPU/gfx10_vdst64_0.rst
new file mode 100644
index 000000000000..6e44c28a07b3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdst64_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vdst96_0.rst b/llvm/docs/AMDGPU/gfx10_vdst96_0.rst
new file mode 100644
index 000000000000..a30e2ee8ae77
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vdst96_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vdst96_0:
+
+vdst
+===========================
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst
new file mode 100644
index 000000000000..1808061d5107
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc128_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vsrc128_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst
new file mode 100644
index 000000000000..95cecb42825c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc32_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vsrc32_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst
new file mode 100644
index 000000000000..fd8c6bd28bda
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst b/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst
new file mode 100644
index 000000000000..56c8fff09eb5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_vsrc64_0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_vsrc64_0:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
new file mode 100644
index 000000000000..e4c4bcdc169f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
@@ -0,0 +1,56 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_waitcnt:
+
+waitcnt
+===========================
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+    ============ ======================================================
+    Bits         Description
+    ============ ======================================================
+    3:0          VM_CNT: vector memory operations count, lower bits.
+    6:4          EXP_CNT: export count.
+    11:8         LGKM_CNT: LDS, GDS, Constant and Message count.
+    15:14        VM_CNT: vector memory operations count, upper bits.
+    ============ ======================================================
+
+This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>`
+or as a combination of the following symbolic helpers:
+
+    ====================== ======================================================================
+    Syntax                 Description
+    ====================== ======================================================================
+    vmcnt(<*N*>)           VM_CNT value. *N* must not exceed the largest VM_CNT value.
+    expcnt(<*N*>)          EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+    lgkmcnt(<*N*>)         LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+    vmcnt_sat(<*N*>)       VM_CNT value computed as min(*N*, the largest VM_CNT value).
+    expcnt_sat(<*N*>)      EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+    lgkmcnt_sat(<*N*>)     LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+    ====================== ======================================================================
+
+These helpers may be specified in any order. Ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+    s_waitcnt 0
+    s_waitcnt vmcnt(1)
+    s_waitcnt expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+    s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
+
diff --git a/llvm/docs/AMDGPU/gfx10_wsdst.rst b/llvm/docs/AMDGPU/gfx10_wsdst.rst
new file mode 100644
index 000000000000..1e39990f8903
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_wsdst.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_wsdst:
+
+sdst
+===========================
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx10_wssrc.rst b/llvm/docs/AMDGPU/gfx10_wssrc.rst
new file mode 100644
index 000000000000..35fdb02a0eac
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_wssrc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_wssrc:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx7_offset_buf.rst b/llvm/docs/AMDGPU/gfx7_offset_buf.rst
index c36df06a7bbf..b78affa6db67 100644
--- a/llvm/docs/AMDGPU/gfx7_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx7_offset_buf.rst
@@ -14,4 +14,4 @@ An unsigned byte offset.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_0.rst b/llvm/docs/AMDGPU/gfx7_src32_0.rst
index 22ff73ddf47d..6a9c977a3a10 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_1.rst b/llvm/docs/AMDGPU/gfx7_src32_1.rst
index 00594597ff17..990d22973c02 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_2.rst b/llvm/docs/AMDGPU/gfx7_src32_2.rst
index b939c4560348..2fdb6462cc40 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_3.rst b/llvm/docs/AMDGPU/gfx7_src32_3.rst
index 83aa9ca71992..19bbde9c7853 100644
--- a/llvm/docs/AMDGPU/gfx7_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx7_src32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_4.rst b/llvm/docs/AMDGPU/gfx7_src32_4.rst
new file mode 100644
index 000000000000..7b0c3a89c1a8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_5.rst b/llvm/docs/AMDGPU/gfx7_src32_5.rst
new file mode 100644
index 000000000000..bcfbaeb013d0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx7_src32_6.rst b/llvm/docs/AMDGPU/gfx7_src32_6.rst
new file mode 100644
index 000000000000..8c49d5954d0d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_src32_6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_src32_6:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_0.rst b/llvm/docs/AMDGPU/gfx7_src64_0.rst
index a19b6ee8bd5a..9088418da5b7 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_1.rst b/llvm/docs/AMDGPU/gfx7_src64_1.rst
index c81864c9573f..feb657c1f5dd 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_src64_2.rst b/llvm/docs/AMDGPU/gfx7_src64_2.rst
index 189245e548df..4a50df7046d9 100644
--- a/llvm/docs/AMDGPU/gfx7_src64_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_src64_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
index 843db249713c..589d9ccd9781 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
index 6e626d836732..4f04b0bc2256 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
index 68a24153b688..2ec4af2f6d55 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
index 669ae4e7e2d0..e07ffe5a9ec2 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_4.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst
new file mode 100644
index 000000000000..71402a7d000e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_5:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst b/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst
new file mode 100644
index 000000000000..32bc30585907
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_ssrc32_6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_ssrc32_6:
+
+ssrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
index 283e7ea63dac..49add61fc94b 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
index 344147fdd279..525593055465 100644
--- a/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx7_ssrc64_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst
new file mode 100644
index 000000000000..063216a5e040
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx8_offset_buf.rst b/llvm/docs/AMDGPU/gfx8_offset_buf.rst
index 42c452416b5b..7b72bb64a3e9 100644
--- a/llvm/docs/AMDGPU/gfx8_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx8_offset_buf.rst
@@ -14,4 +14,4 @@ An unsigned byte offset.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_0.rst b/llvm/docs/AMDGPU/gfx8_src32_0.rst
index a9c11fea8e3b..2e4d42b35f29 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_1.rst b/llvm/docs/AMDGPU/gfx8_src32_1.rst
index 67dcdc8ed5e9..ea64ab1a9225 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_2.rst b/llvm/docs/AMDGPU/gfx8_src32_2.rst
new file mode 100644
index 000000000000..016e7b9b5285
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_3.rst b/llvm/docs/AMDGPU/gfx8_src32_3.rst
new file mode 100644
index 000000000000..ea3164d08b08
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src64_0.rst b/llvm/docs/AMDGPU/gfx8_src64_0.rst
index 573fd68b2a11..d62c37e3b60a 100644
--- a/llvm/docs/AMDGPU/gfx8_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_src64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src64_1.rst b/llvm/docs/AMDGPU/gfx8_src64_1.rst
index d2c78b754d7e..cd5ab8b1b75d 100644
--- a/llvm/docs/AMDGPU/gfx8_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx8_src64_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
index 82d18b158537..1f7d9fbdb23e 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
index 02d90a4d1da4..eb5e2247fe04 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc32_4.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
index b8389dcdbae1..6c7efe5d5308 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
index 209dffc8da03..3252202ce988 100644
--- a/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx8_ssrc64_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst
new file mode 100644
index 000000000000..5ed15a15226d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx9_msg.rst b/llvm/docs/AMDGPU/gfx9_msg.rst
index f18cff46ecb2..898848532c17 100644
--- a/llvm/docs/AMDGPU/gfx9_msg.rst
+++ b/llvm/docs/AMDGPU/gfx9_msg.rst
@@ -52,6 +52,7 @@ Each message type supports specific operations:
     \                            GS_OP_CUT                      1            Optional
     \                            GS_OP_EMIT                     2            Optional
     \                            GS_OP_EMIT_CUT                 3            Optional
+    MSG_GS_ALLOC_REQ  9          \-                             \-           \-
     MSG_SYSMSG        15         SYSMSG_OP_ECC_ERR_INTERRUPT    1            \-
     \                            SYSMSG_OP_REG_RD               2            \-
     \                            SYSMSG_OP_HOST_TRAP_ACK        3            \-
diff --git a/llvm/docs/AMDGPU/gfx9_offset_buf.rst b/llvm/docs/AMDGPU/gfx9_offset_buf.rst
index ec6cc330072e..7a01fde7f3c1 100644
--- a/llvm/docs/AMDGPU/gfx9_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx9_offset_buf.rst
@@ -14,4 +14,4 @@ An unsigned byte offset.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_0.rst b/llvm/docs/AMDGPU/gfx9_src32_0.rst
index 288ccbb37d09..d4c495841c04 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_1.rst b/llvm/docs/AMDGPU/gfx9_src32_1.rst
index a06764da8b22..b96594c55041 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_2.rst b/llvm/docs/AMDGPU/gfx9_src32_2.rst
new file mode 100644
index 000000000000..045b913a1293
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_3.rst b/llvm/docs/AMDGPU/gfx9_src32_3.rst
new file mode 100644
index 000000000000..2bb797215c2b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_0.rst b/llvm/docs/AMDGPU/gfx9_src64_0.rst
index f8ef842ef4f1..cc6e5ca16565 100644
--- a/llvm/docs/AMDGPU/gfx9_src64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_src64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src64_1.rst b/llvm/docs/AMDGPU/gfx9_src64_1.rst
index fe7b7fda1f5e..9075c24085f3 100644
--- a/llvm/docs/AMDGPU/gfx9_src64_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src64_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
index 25d6b3744fd6..d52f6880b713 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst b/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
index 7e5542737bd8..b151fbb1bd15 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc32_4.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
index b2f86e11cb0d..4a3ef065a9b5 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst b/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
index 72d2c46d3a9b..a9aa6dc8a4a3 100644
--- a/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_ssrc64_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst b/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
new file mode 100644
index 000000000000..5a5b9218e160
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_vsrc32_1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_vsrc32_1:
+
+vsrc
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPUInstructionSyntax.rst b/llvm/docs/AMDGPUInstructionSyntax.rst
index 90ad54aade83..588635023cbf 100644
--- a/llvm/docs/AMDGPUInstructionSyntax.rst
+++ b/llvm/docs/AMDGPUInstructionSyntax.rst
@@ -153,6 +153,7 @@ For detailed information about operands follow *operand links* in GPU-specific d
 * :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
 * :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
 * :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
 
 Modifiers
 =========
@@ -167,4 +168,5 @@ Information about modifiers supported for individual instructions may be found i
 * :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
 * :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
 * :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
 
diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst
index 1a555b678324..d66e94dcb91a 100644
--- a/llvm/docs/AMDGPUModifierSyntax.rst
+++ b/llvm/docs/AMDGPUModifierSyntax.rst
@@ -73,8 +73,8 @@ Examples:
 
 .. _amdgpu_synid_sw_offset16:
 
-pattern
-~~~~~~~
+swizzle pattern
+~~~~~~~~~~~~~~~
 
 This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
 It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.
@@ -165,8 +165,8 @@ EXP Modifiers
 done
 ~~~~
 
-Specifies if this is the last export from the shader to the target. By default, current
-instruction does not finish an export sequence.
+Specifies if this is the last export from the shader to the target. By default,
+*exp* instruction does not finish an export sequence.
 
     ======================================== ================================================
     Syntax                                   Description
@@ -249,11 +249,71 @@ Examples:
   offset:-4000
   offset:0x10
 
+.. _amdgpu_synid_flat_offset12s:
+
+offset12s
+~~~~~~~~~
+
+Specifies an immediate signed 12-bit offset, in bytes. The default value is 0.
+
+Can be used with *global/scratch* opcodes only.
+
+GFX10 only.
+
+    ============================ =======================================================
+    Syntax                       Description
+    ============================ =======================================================
+    offset:{-2048..2047}         Specifies a 12-bit signed offset as an
+                                 :ref:`integer number <amdgpu_synid_integer_number>`.
+    ============================ =======================================================
+
+Examples:
+
+.. parsed-literal::
+
+  offset:-2000
+  offset:0x10
+
+.. _amdgpu_synid_flat_offset11:
+
+offset11
+~~~~~~~~
+
+Specifies an immediate unsigned 11-bit offset, in bytes. The default value is 0.
+
+Cannot be used with *global/scratch* opcodes.
+
+GFX10 only.
+
+    ================= ======================================================
+    Syntax            Description
+    ================= ======================================================
+    offset:{0..2047}  Specifies an 11-bit unsigned offset as a positive
+                      :ref:`integer number <amdgpu_synid_integer_number>`.
+    ================= ======================================================
+
+Examples:
+
+.. parsed-literal::
+
+  offset:2047
+  offset:0xff
+
+dlc
+~~~
+
+See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
+
 glc
 ~~~
 
 See a description :ref:`here<amdgpu_synid_glc>`.
 
+lds
+~~~
+
+See a description :ref:`here<amdgpu_synid_lds>`. GFX10 only.
+
 slc
 ~~~
 
@@ -345,7 +405,7 @@ r128
 
 Specifies texture resource size. The default size is 256 bits.
 
-GFX7 and GFX8 only.
+GFX7, GFX8 and GFX10 only.
 
     =================== ================================================
     Syntax              Description
@@ -407,7 +467,7 @@ Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
                                              Note that GFX8.0 does not support data packing.
                                              Each 16-bit data element occupies 1 VGPR.
 
-                                             GFX8.1 and GFX9 support data packing.
+                                             GFX8.1, GFX9 and GFX10 support data packing.
                                              Each pair of 16-bit data elements 
                                              occupies 1 VGPR.
     ======================================== ================================================
@@ -417,7 +477,8 @@ Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
 a16
 ~~~
 
-Specifies size of image address components: 16 or 32 bits (32 bits by default). GFX9 only.
+Specifies size of image address components: 16 or 32 bits (32 bits by default).
+GFX9 and GFX10 only.
 
     ======================================== ================================================
     Syntax                                   Description
@@ -425,9 +486,69 @@ Specifies size of image address components: 16 or 32 bits (32 bits by default).
     a16                                      Enables 16-bits image address components.
     ======================================== ================================================
 
+.. _amdgpu_synid_dim:
+
+dim
+~~~
+
+Specifies surface dimension. This is a mandatory modifier. There is no default value.
+
+GFX10 only.
+
+    =============================== =========================================================
+    Syntax                          Description
+    =============================== =========================================================
+    dim:1D                          One-dimensional image.
+    dim:2D                          Two-dimensional image.
+    dim:3D                          Three-dimensional image.
+    dim:CUBE                        Cubemap array.
+    dim:1D_ARRAY                    One-dimensional image array.
+    dim:2D_ARRAY                    Two-dimensional image array.
+    dim:2D_MSAA                     Two-dimensional multi-sample auto-aliasing image.
+    dim:2D_MSAA_ARRAY               Two-dimensional multi-sample auto-aliasing image array.
+    =============================== =========================================================
+
+The following table defines an alternative syntax which is supported
+for compatibility with SP3 assembler:
+
+    =============================== =========================================================
+    Syntax                          Description
+    =============================== =========================================================
+    dim:SQ_RSRC_IMG_1D              One-dimensional image.
+    dim:SQ_RSRC_IMG_2D              Two-dimensional image.
+    dim:SQ_RSRC_IMG_3D              Three-dimensional image.
+    dim:SQ_RSRC_IMG_CUBE            Cubemap array.
+    dim:SQ_RSRC_IMG_1D_ARRAY        One-dimensional image array.
+    dim:SQ_RSRC_IMG_2D_ARRAY        Two-dimensional image array.
+    dim:SQ_RSRC_IMG_2D_MSAA         Two-dimensional multi-sample auto-aliasing image.
+    dim:SQ_RSRC_IMG_2D_MSAA_ARRAY   Two-dimensional multi-sample auto-aliasing image array.
+    =============================== =========================================================
+
+dlc
+~~~
+
+See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
+
 Miscellaneous Modifiers
 -----------------------
 
+.. _amdgpu_synid_dlc:
+
+dlc
+~~~
+
+Controls device level cache policy for memory operations. Used for synchronization.
+When specified, forces operation to bypass device level cache making the operation device
+level coherent. By default, instructions use device level cache.
+
+GFX10 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    dlc                                      Bypass device level cache.
+    ======================================== ================================================
+
 .. _amdgpu_synid_glc:
 
 glc
@@ -444,6 +565,35 @@ See AMD documentation for details.
     glc                                      Set glc bit to 1.
     ======================================== ================================================
 
+.. _amdgpu_synid_lds:
+
+lds
+~~~
+
+Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+
+    ======================================== ===========================
+    Syntax                                   Description
+    ======================================== ===========================
+    lds                                      Store result in LDS.
+    ======================================== ===========================
+
+.. _amdgpu_synid_nv:
+
+nv
+~~
+
+Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
+
+GFX9 only.
+
+    ======================================== ================================================
+    Syntax                                   Description
+    ======================================== ================================================
+    nv                                       Indicates that instruction operates on
+                                             non-volatile memory.
+    ======================================== ================================================
+
 .. _amdgpu_synid_slc:
 
 slc
@@ -474,22 +624,6 @@ See AMD documentation for details.
     tfe                                      Set tfe bit to 1.
     ======================================== ================================================
 
-.. _amdgpu_synid_nv:
-
-nv
-~~
-
-Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
-
-GFX9 only.
-
-    ======================================== ================================================
-    Syntax                                   Description
-    ======================================== ================================================
-    nv                                       Indicates that instruction operates on
-                                             non-volatile memory.
-    ======================================== ================================================
-
 MUBUF/MTBUF Modifiers
 ---------------------
 
@@ -574,18 +708,15 @@ slc
 
 See a description :ref:`here<amdgpu_synid_slc>`.
 
-.. _amdgpu_synid_lds:
-
 lds
 ~~~
 
-Specifies where to store the result: VGPRs or LDS (VGPRs by default).
+See a description :ref:`here<amdgpu_synid_lds>`.
 
-    ======================================== ===========================
-    Syntax                                   Description
-    ======================================== ===========================
-    lds                                      Store result in LDS.
-    ======================================== ===========================
+dlc
+~~~
+
+See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
 
 tfe
 ~~~
@@ -617,7 +748,12 @@ See a description :ref:`here<amdgpu_synid_glc>`.
 nv
 ~~
 
-See a description :ref:`here<amdgpu_synid_nv>`.
+See a description :ref:`here<amdgpu_synid_nv>`. GFX9 only.
+
+dlc
+~~~
+
+See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
 
 VINTRP Modifiers
 ----------------
@@ -628,7 +764,7 @@ high
 ~~~~
 
 Specifies which half of the LDS word to use. Low half of LDS word is used by default.
-GFX9 only.
+GFX9 and GFX10 only.
 
     ======================================== ================================
     Syntax                                   Description
@@ -636,10 +772,60 @@ GFX9 only.
     high                                     Use high half of LDS word.
     ======================================== ================================
 
-VOP1/VOP2 DPP Modifiers
------------------------
+DPP8 Modifiers
+--------------
 
-GFX8 and GFX9 only.
+GFX10 only.
+
+.. _amdgpu_synid_dpp8_sel:
+
+dpp8_sel
+~~~~~~~~
+
+Selects which lane to pull data from, within a group of 8 lanes. This is a mandatory modifier.
+There is no default value.
+
+GFX10 only.
+
+The *dpp8_sel* modifier must specify exactly 8 values, each ranging from 0 to 7.
+First value selects which lane to read from to supply data into lane 0.
+Second value controls value for lane 1 and so on.
+
+    =============================================================== ===========================
+    Syntax                                                          Description
+    =============================================================== ===========================
+    dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}]  Select lanes to read from.
+    =============================================================== ===========================
+
+Examples:
+
+.. parsed-literal::
+
+  dpp8:[7,6,5,4,3,2,1,0]
+  dpp8:[0,1,0,1,0,1,0,1]
+
+.. _amdgpu_synid_fi8:
+
+fi
+~~
+
+Controls interaction with inactive lanes for *dpp8* instructions. The default value is zero.
+
+Note. *Inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
+
+GFX10 only.
+
+    ==================================== =====================================================
+    Syntax                               Description
+    ==================================== =====================================================
+    fi:0                                 Fetch zero when accessing data from inactive lanes.
+    fi:1                                 Fetch pre-exist values from inactive lanes.
+    ==================================== =====================================================
+
+DPP/DPP16 Modifiers
+-------------------
+
+GFX8, GFX9 and GFX10 only.
 
 .. _amdgpu_synid_dpp_ctrl:
 
@@ -649,7 +835,9 @@ dpp_ctrl
 Specifies how data are shared between threads. This is a mandatory modifier.
 There is no default value.
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+GFX8 and GFX9 only. Use :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` for GFX10.
+
+Note. The lanes of a wavefront are organized in four *rows* and four *banks*.
 
     ======================================== ================================================
     Syntax                                   Description
@@ -674,6 +862,44 @@ Note: Numeric parameters may be specified as either
 
 Examples:
 
+.. parsed-literal::
+
+  quad_perm:[0, 1, 2, 3]
+  row_shl:3
+
+.. _amdgpu_synid_dpp16_ctrl:
+
+dpp16_ctrl
+~~~~~~~~~~
+
+Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.
+
+GFX10 only. Use :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` for GFX8 and GFX9.
+
+Note. The lanes of a wavefront are organized in four *rows* and four *banks*.
+(There are only two rows in *wave32* mode.)
+
+    ======================================== ====================================================
+    Syntax                                   Description
+    ======================================== ====================================================
+    quad_perm:[{0..3},{0..3},{0..3},{0..3}]  Full permute of 4 threads.
+    row_mirror                               Mirror threads within row.
+    row_half_mirror                          Mirror threads within 1/2 row (8 threads).
+    row_share:{0..15}                        Share the value from the specified lane with other
+                                             lanes in the row.
+    row_xmask:{0..15}                        Fetch from XOR(current lane id, specified lane id).
+    row_shl:{1..15}                          Row shift left by 1-15 threads.
+    row_shr:{1..15}                          Row shift right by 1-15 threads.
+    row_ror:{1..15}                          Row rotate right by 1-15 threads.
+    ======================================== ====================================================
+
+Note: Numeric parameters may be specified as either
+:ref:`integer numbers<amdgpu_synid_integer_number>` or
+:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
 .. parsed-literal::
 
   quad_perm:[0, 1, 2, 3]
@@ -686,7 +912,8 @@ row_mask
 
 Controls which rows are enabled for data sharing. By default, all rows are enabled.
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+Note. The lanes of a wavefront are organized in four *rows* and four *banks*.
+(There are only two rows in *wave32* mode.)
 
     ======================================== =====================================================
     Syntax                                   Description
@@ -696,6 +923,9 @@ Note. The lanes of a wavefront are organized in four banks and four rows.
 
                                              Each of 4 bits in the mask controls one
                                              row (0 - disabled, 1 - enabled).
+
+                                             In *wave32* mode the values should be limited to
+                                             {0..7}.
     ======================================== =====================================================
 
 Examples:
@@ -713,7 +943,8 @@ bank_mask
 
 Controls which banks are enabled for data sharing. By default, all banks are enabled.
 
-Note. The lanes of a wavefront are organized in four banks and four rows.
+Note. The lanes of a wavefront are organized in four *rows* and four *banks*.
+(There are only two rows in *wave32* mode.)
 
     ======================================== =======================================================
     Syntax                                   Description
@@ -750,10 +981,30 @@ invalid lanes is disabled.
                                              return zero.
     ======================================== ================================================
 
-VOP1/VOP2/VOPC SDWA Modifiers
------------------------------
+.. _amdgpu_synid_fi16:
 
-GFX8 and GFX9 only.
+fi
+~~
+
+Controls interaction with *inactive* lanes for *dpp16* instructions. The default value is zero.
+
+Note. *Inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
+
+GFX10 only.
+
+    ======================================== ==================================================
+    Syntax                                   Description
+    ======================================== ==================================================
+    fi:0                                     Interaction with inactive lanes is controlled by
+                                             :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.
+
+    fi:1                                     Fetch pre-exist values from inactive lanes.
+    ======================================== ==================================================
+
+SDWA Modifiers
+--------------
+
+GFX8, GFX9 and GFX10 only.
 
 clamp
 ~~~~~
@@ -765,7 +1016,7 @@ omod
 
 See a description :ref:`here<amdgpu_synid_omod>`.
 
-GFX9 only.
+GFX9 and GFX10 only.
 
 .. _amdgpu_synid_dst_sel:
 
@@ -844,12 +1095,12 @@ Controls which bits in the src1 are used. By default, all bits are used.
 
 .. _amdgpu_synid_sdwa_operand_modifiers:
 
-VOP1/VOP2/VOPC SDWA Operand Modifiers
--------------------------------------
+SDWA Operand Modifiers
+----------------------
 
 Operand modifiers are not used separately. They are applied to source operands.
 
-GFX8 and GFX9 only.
+GFX8, GFX9 and GFX10 only.
 
 abs
 ~~~
@@ -903,7 +1154,7 @@ The value 0 selects the low bits, while 1 selects the high bits.
 Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
 by op_sel must be 0.
 
-GFX9 only.
+GFX9 and GFX10 only.
 
     ======================================== ============================================================
     Syntax                                   Description
@@ -1029,7 +1280,7 @@ This section describes modifiers of *regular* VOP3P instructions.
 *v_mad_mix_f32*, *v_mad_mixhi_f16* and *v_mad_mixlo_f16*
 instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`.
 
-GFX9 only.
+GFX9 and GFX10 only.
 
 .. _amdgpu_synid_op_sel:
 
@@ -1173,7 +1424,7 @@ in a manner different from *regular* VOP3P instructions.
 
 See a description below.
 
-GFX9 only.
+GFX9 and GFX10 only.
 
 .. _amdgpu_synid_mad_mix_op_sel:
 
diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index 8713c72a2536..523c5ac7179c 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -75,6 +75,30 @@ Examples:
   [v252]
   [v252,v253,v254,v255]
 
+.. _amdgpu_synid_nsa:
+
+*Image* instructions may use special *NSA* (Non-Sequential Address) syntax for *image addresses*:
+
+    =================================================== ====================================================================
+    Syntax                                              Description
+    =================================================== ====================================================================
+    **[v**\ <A>, \ **v**\ <B>, ... **v**\ <X>\ **]**    A sequence of *vector* registers. At least one register
+                                                        must be specified.
+
+                                                        In contrast with standard syntax described above, registers in
+                                                        this sequence are not required to have consecutive indices.
+                                                        Moreover, the same register may appear in the list more than once.
+    =================================================== ====================================================================
+
+Note. Reqister indices must be in the range 0..255. They must be specified as decimal integer numbers.
+
+Examples:
+
+.. parsed-literal::
+
+  [v32,v1,v2]
+  [v4,v4,v4,v4]
+
 .. _amdgpu_synid_s:
 
 s
@@ -88,6 +112,7 @@ Scalar 32-bit registers. The number of available *scalar* registers depends on G
     GFX7    104
     GFX8    102
     GFX9    102
+    GFX10   106
     ======= ============================
 
 A sequence of *scalar* registers may be used to operate with more than 32 bits of data.
@@ -171,6 +196,7 @@ The number of available *ttmp* registers depends on GPU:
     GFX7    12
     GFX8    12
     GFX9    16
+    GFX10   16
     ======= ===========================
 
 A sequence of *ttmp* registers may be used to operate with more than 32 bits of data.
@@ -255,7 +281,7 @@ High and low 32 bits of *trap base address* may be accessed as separate register
     [tba_hi]           High 32 bits of *trap base address* register (an alternative syntax).   GFX7, GFX8
     ================== ======================================================================= =============
 
-Note that *tba*, *tba_lo* and *tba_hi* are not accessible as assembler registers in GFX9,
+Note that *tba*, *tba_lo* and *tba_hi* are not accessible as assembler registers in GFX9 and GFX10,
 but *tba* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
 
 .. _amdgpu_synid_tma:
@@ -284,7 +310,7 @@ High and low 32 bits of *trap memory address* may be accessed as separate regist
     [tma_hi]          High 32 bits of *trap memory address* register (an alternative syntax). GFX7, GFX8
     ================= ======================================================================= ==================
 
-Note that *tma*, *tma_lo* and *tma_hi* are not accessible as assembler registers in GFX9,
+Note that *tma*, *tma_lo* and *tma_hi* are not accessible as assembler registers in GFX9 and GFX10,
 but *tma* is readable/writable with the help of *s_get_reg* and *s_set_reg* instructions.
 
 .. _amdgpu_synid_flat_scratch:
@@ -321,7 +347,7 @@ xnack
 Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
 received an *XNACK* due to a vector memory operation.
 
-.. WARNING:: GFX7 does not support *xnack* feature. Not all GFX8 and GFX9 :ref:`processors<amdgpu-processors>` support *xnack* feature.
+.. WARNING:: GFX7 does not support *xnack* feature. For availability of this feature in other GPUs, refer :ref:`this table<amdgpu-processors>`.
 
 \
 
@@ -345,6 +371,7 @@ High and low 32 bits of *xnack mask* may be accessed as separate registers:
     ===================== ==============================================================
 
 .. _amdgpu_synid_vcc:
+.. _amdgpu_synid_vcc_lo:
 
 vcc
 ---
@@ -352,6 +379,8 @@ vcc
 Vector condition code, 64-bits wide. A bit mask with one bit per thread;
 it holds the result of a vector compare operation.
 
+Note that GFX10 H/W does not use high 32 bits of *vcc* in *wave32* mode.
+
     ================ =========================================================================
     Syntax           Description
     ================ =========================================================================
@@ -395,6 +424,8 @@ Execute mask, 64-bits wide. A bit mask with one bit per thread,
 which is applied to vector instructions and controls which threads execute
 and which ignore the instruction.
 
+Note that GFX10 H/W does not use high 32 bits of *exec* in *wave32* mode.
+
     ===================== =================================================================
     Syntax                Description
     ===================== =================================================================
@@ -419,9 +450,9 @@ High and low 32 bits of *execute mask* may be accessed as separate registers:
 vccz
 ----
 
-A single bit-flag indicating that the :ref:`vcc<amdgpu_synid_vcc>` is all zeros.
+A single bit flag indicating that the :ref:`vcc<amdgpu_synid_vcc>` is all zeros.
 
-.. WARNING:: This operand is not currently supported by AMDGPU assembler.
+Note. When GFX10 operates in *wave32* mode, this register reflects state of :ref:`vcc_lo<amdgpu_synid_vcc_lo>`.
 
 .. _amdgpu_synid_execz:
 
@@ -430,7 +461,7 @@ execz
 
 A single bit flag indicating that the :ref:`exec<amdgpu_synid_exec>` is all zeros.
 
-.. WARNING:: This operand is not currently supported by AMDGPU assembler.
+Note. When GFX10 operates in *wave32* mode, this register reflects state of :ref:`exec_lo<amdgpu_synid_exec>`.
 
 .. _amdgpu_synid_scc:
 
@@ -439,7 +470,7 @@ scc
 
 A single bit flag indicating the result of a scalar compare operation.
 
-.. WARNING:: This operand is not currently supported by AMDGPU assembler.
+.. _amdgpu_synid_lds_direct:
 
 lds_direct
 ----------
@@ -447,29 +478,43 @@ lds_direct
 A special operand which supplies a 32-bit value
 fetched from *LDS* memory using :ref:`m0<amdgpu_synid_m0>` as an address.
 
-.. WARNING:: This operand is not currently supported by AMDGPU assembler.
+.. _amdgpu_synid_null:
+
+null
+----
+
+This is a special operand which may be used as a source or a destination.
+
+When used as a destination, the result of the operation is discarded.
+
+When used as a source, it supplies zero value.
+
+GFX10 only.
+
+.. WARNING:: Due to a H/W bug, this operand cannot be used with VALU instructions in first generation of GFX10.
 
 .. _amdgpu_synid_constant:
 
 constant
 --------
 
-A set of integer and floating-point *inline constants*:
+A set of integer and floating-point *inline* constants and values:
 
 * :ref:`iconst<amdgpu_synid_iconst>`
 * :ref:`fconst<amdgpu_synid_fconst>`
+* :ref:`ival<amdgpu_synid_ival>`
 
-These operands are encoded as a part of instruction.
+In contrast with :ref:`literals<amdgpu_synid_literal>`, these operands are encoded as a part of instruction.
 
 If a number may be encoded as either
 a :ref:`literal<amdgpu_synid_literal>` or 
-an :ref:`inline constant<amdgpu_synid_constant>`,
+a :ref:`constant<amdgpu_synid_constant>`,
 assembler selects the latter encoding as more efficient.
 
 .. _amdgpu_synid_iconst:
 
 iconst
-------
+~~~~~~
 
 An :ref:`integer number<amdgpu_synid_integer_number>`
 encoded as an *inline constant*.
@@ -491,26 +536,10 @@ as described :ref:`here<amdgpu_synid_int_const_conv>`.
 
 .. WARNING:: GFX7 does not support inline constants for *f16* operands.
 
-There are also symbolic inline constants which provide read-only access to H/W registers.
-
-.. WARNING:: These inline constants are not currently supported by AMDGPU assembler.
-
-\
-
-    ======================== ================================================ =============
-    Syntax                   Note                                             Availability
-    ======================== ================================================ =============
-    shared_base              Base address of shared memory region.            GFX9
-    shared_limit             Address of the end of shared memory region.      GFX9
-    private_base             Base address of private memory region.           GFX9
-    private_limit            Address of the end of private memory region.     GFX9
-    pops_exiting_wave_id     A dedicated counter for POPS.                    GFX9
-    ======================== ================================================ =============
-
 .. _amdgpu_synid_fconst:
 
 fconst
-------
+~~~~~~
 
 A :ref:`floating-point number<amdgpu_synid_floating-point_number>`
 encoded as an *inline constant*.
@@ -535,13 +564,31 @@ as described :ref:`here<amdgpu_synid_fp_const_conv>`.
     -1.0                  Floating-point constant -1.0                          All GPUs
     -2.0                  Floating-point constant -2.0                          All GPUs
     -4.0                  Floating-point constant -4.0                          All GPUs
-    0.1592                1.0/(2.0*pi). Use only for 16-bit operands.           GFX8, GFX9
-    0.15915494            1.0/(2.0*pi). Use only for 16- and 32-bit operands.   GFX8, GFX9
-    0.15915494309189532   1.0/(2.0*pi).                                         GFX8, GFX9
+    0.1592                1.0/(2.0*pi). Use only for 16-bit operands.           GFX8, GFX9, GFX10
+    0.15915494            1.0/(2.0*pi). Use only for 16- and 32-bit operands.   GFX8, GFX9, GFX10
+    0.15915494309189532   1.0/(2.0*pi).                                         GFX8, GFX9, GFX10
     ===================== ===================================================== ==================
 
 .. WARNING:: GFX7 does not support inline constants for *f16* operands.
 
+.. _amdgpu_synid_ival:
+
+ival
+~~~~
+
+A symbolic operand encoded as an *inline constant*.
+These operands provide read-only access to H/W registers.
+
+    ======================== ================================================ =============
+    Syntax                   Note                                             Availability
+    ======================== ================================================ =============
+    shared_base              Base address of shared memory region.            GFX9, GFX10
+    shared_limit             Address of the end of shared memory region.      GFX9, GFX10
+    private_base             Base address of private memory region.           GFX9, GFX10
+    private_limit            Address of the end of private memory region.     GFX9, GFX10
+    pops_exiting_wave_id     A dedicated counter for POPS.                    GFX9, GFX10
+    ======================== ================================================ =============
+
 .. _amdgpu_synid_literal:
 
 literal
@@ -604,7 +651,7 @@ simm21
 
 A 21-bit :ref:`integer number<amdgpu_synid_integer_number>`.
 
-.. WARNING:: Assembler currently supports 20-bit unsigned offsets only .Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
+.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` as a replacement.
 
 .. _amdgpu_synid_off:
 
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index f90b0d479827..7b595cd937e6 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -5738,14 +5738,12 @@ Instructions
    AMDGPU/AMDGPUAsmGFX7
    AMDGPU/AMDGPUAsmGFX8
    AMDGPU/AMDGPUAsmGFX9
+   AMDGPU/AMDGPUAsmGFX10
    AMDGPUModifierSyntax
    AMDGPUOperandSyntax
    AMDGPUInstructionSyntax
    AMDGPUInstructionNotation
 
-.. TODO
-   AMDGPUAsmGFX10
-
 An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
 
     ``<``\ *opcode*\ ``>    <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,...    <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
@@ -5757,7 +5755,8 @@ The order of *operands* and *modifiers* is fixed.
 Most *modifiers* are optional and may be omitted.
 
 See detailed instruction syntax description for :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`,
-:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`.
+:doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`, :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
+and :doc:`GFX9<AMDGPU/AMDGPUAsmGFX10>`.
 
 Note that features under development are not included in this description.