Revert r315885: [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_indexed*
MSVC doesn't like one of the constructors. llvm-svn: 315886
This commit is contained in:
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ce72d611af
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@ -341,12 +341,6 @@ protected:
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bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
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bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const;
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const MachineRegisterInfo &MRI) const;
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/// Return true if the specified operand is a G_GEP with a G_CONSTANT on the
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/// right-hand side. GlobalISel's separation of pointer and integer types
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/// means that we don't need to worry about G_OR with equivalent semantics.
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bool isBaseWithConstantOffset(const MachineOperand &Root,
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const MachineRegisterInfo &MRI) const;
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bool isObviouslySafeToFold(MachineInstr &MI) const;
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bool isObviouslySafeToFold(MachineInstr &MI) const;
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};
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};
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@ -248,20 +248,10 @@ bool InstructionSelector::executeMatchTable(
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int64_t InsnID = MatchTable[CurrentIdx++];
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int64_t InsnID = MatchTable[CurrentIdx++];
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int64_t OpIdx = MatchTable[CurrentIdx++];
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int64_t OpIdx = MatchTable[CurrentIdx++];
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int64_t SizeInBits = MatchTable[CurrentIdx++];
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int64_t SizeInBits = MatchTable[CurrentIdx++];
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DEBUG(dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs[" << InsnID
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DEBUG(dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs[" << InsnID
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<< "]->getOperand(" << OpIdx
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<< "]->getOperand(" << OpIdx
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<< "), SizeInBits=" << SizeInBits << ")\n");
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<< "), SizeInBits=" << SizeInBits << ")\n");
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assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
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assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
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// iPTR must be looked up in the target.
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if (SizeInBits == 0) {
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MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
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SizeInBits = MF->getDataLayout().getPointerSizeInBits(0);
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}
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assert(SizeInBits != 0 && "Pointer size must be known");
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const LLT &Ty = MRI.getType(State.MIs[InsnID]->getOperand(OpIdx).getReg());
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const LLT &Ty = MRI.getType(State.MIs[InsnID]->getOperand(OpIdx).getReg());
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if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits) {
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if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits) {
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if (handleReject() == RejectAndGiveUp)
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if (handleReject() == RejectAndGiveUp)
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@ -18,7 +18,6 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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@ -99,23 +98,6 @@ bool InstructionSelector::isOperandImmEqual(
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return false;
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return false;
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}
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}
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bool InstructionSelector::isBaseWithConstantOffset(
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const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
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if (!Root.isReg())
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return false;
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MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
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if (RootI->getOpcode() != TargetOpcode::G_GEP)
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return false;
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MachineOperand &RHS = RootI->getOperand(2);
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MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
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if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
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return true;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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@ -2516,22 +2516,6 @@ def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
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def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
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def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
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def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
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def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
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def gi_am_indexed8 :
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GIComplexOperandMatcher<s64, "selectAddrModeIndexed<8>">,
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GIComplexPatternEquiv<am_indexed8>;
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def gi_am_indexed16 :
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GIComplexOperandMatcher<s64, "selectAddrModeIndexed<16>">,
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GIComplexPatternEquiv<am_indexed16>;
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def gi_am_indexed32 :
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GIComplexOperandMatcher<s64, "selectAddrModeIndexed<32>">,
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GIComplexPatternEquiv<am_indexed32>;
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def gi_am_indexed64 :
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GIComplexOperandMatcher<s64, "selectAddrModeIndexed<64>">,
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GIComplexPatternEquiv<am_indexed64>;
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def gi_am_indexed128 :
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GIComplexOperandMatcher<s64, "selectAddrModeIndexed<128>">,
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GIComplexPatternEquiv<am_indexed128>;
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class UImm12OffsetOperand<int Scale> : AsmOperandClass {
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class UImm12OffsetOperand<int Scale> : AsmOperandClass {
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let Name = "UImm12Offset" # Scale;
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let Name = "UImm12Offset" # Scale;
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let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
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let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
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@ -3162,23 +3146,6 @@ def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
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def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
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def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
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def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
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def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
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def gi_am_unscaled8 :
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GIComplexOperandMatcher<s64, "selectAddrModeUnscaled8">,
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GIComplexPatternEquiv<am_unscaled8>;
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def gi_am_unscaled16 :
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GIComplexOperandMatcher<s64, "selectAddrModeUnscaled16">,
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GIComplexPatternEquiv<am_unscaled16>;
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def gi_am_unscaled32 :
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GIComplexOperandMatcher<s64, "selectAddrModeUnscaled32">,
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GIComplexPatternEquiv<am_unscaled32>;
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def gi_am_unscaled64 :
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GIComplexOperandMatcher<s64, "selectAddrModeUnscaled64">,
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GIComplexPatternEquiv<am_unscaled64>;
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def gi_am_unscaled128 :
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GIComplexOperandMatcher<s64, "selectAddrModeUnscaled128">,
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GIComplexPatternEquiv<am_unscaled128>;
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class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
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class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
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string asm, list<dag> pattern>
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string asm, list<dag> pattern>
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: I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
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: I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
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@ -66,32 +66,6 @@ private:
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ComplexRendererFn selectArithImmed(MachineOperand &Root) const;
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ComplexRendererFn selectArithImmed(MachineOperand &Root) const;
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ComplexRendererFn selectAddrModeUnscaled(MachineOperand &Root,
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unsigned Size) const;
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ComplexRendererFn selectAddrModeUnscaled8(MachineOperand &Root) const {
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return selectAddrModeUnscaled(Root, 1);
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}
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ComplexRendererFn selectAddrModeUnscaled16(MachineOperand &Root) const {
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return selectAddrModeUnscaled(Root, 2);
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}
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ComplexRendererFn selectAddrModeUnscaled32(MachineOperand &Root) const {
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return selectAddrModeUnscaled(Root, 4);
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}
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ComplexRendererFn selectAddrModeUnscaled64(MachineOperand &Root) const {
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return selectAddrModeUnscaled(Root, 8);
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}
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ComplexRendererFn selectAddrModeUnscaled128(MachineOperand &Root) const {
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return selectAddrModeUnscaled(Root, 16);
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}
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ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root,
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unsigned Size) const;
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template <int Width>
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ComplexRendererFn selectAddrModeIndexed(MachineOperand &Root) const {
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return selectAddrModeIndexed(Root, Width / 8);
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}
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const AArch64TargetMachine &TM;
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const AArch64TargetMachine &TM;
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const AArch64Subtarget &STI;
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const AArch64Subtarget &STI;
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const AArch64InstrInfo &TII;
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const AArch64InstrInfo &TII;
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@ -1418,105 +1392,6 @@ AArch64InstructionSelector::selectArithImmed(MachineOperand &Root) const {
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}};
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}};
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}
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}
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/// Select a "register plus unscaled signed 9-bit immediate" address. This
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/// should only match when there is an offset that is not valid for a scaled
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/// immediate addressing mode. The "Size" argument is the size in bytes of the
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/// memory reference, which is needed here to know what is valid for a scaled
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/// immediate.
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InstructionSelector::ComplexRendererFn
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AArch64InstructionSelector::selectAddrModeUnscaled(MachineOperand &Root,
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unsigned Size) const {
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MachineRegisterInfo &MRI =
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Root.getParent()->getParent()->getParent()->getRegInfo();
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if (!Root.isReg())
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return None;
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if (!isBaseWithConstantOffset(Root, MRI))
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return None;
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MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
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if (!RootDef)
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return None;
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MachineOperand &OffImm = RootDef->getOperand(2);
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if (!OffImm.isReg())
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return None;
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MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg());
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if (!RHS || RHS->getOpcode() != TargetOpcode::G_CONSTANT)
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return None;
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int64_t RHSC;
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MachineOperand &RHSOp1 = RHS->getOperand(1);
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if (!RHSOp1.isCImm() || RHSOp1.getCImm()->getBitWidth() > 64)
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return None;
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RHSC = RHSOp1.getCImm()->getSExtValue();
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// If the offset is valid as a scaled immediate, don't match here.
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if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Log2_32(Size)))
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return None;
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if (RHSC >= -256 && RHSC < 256) {
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MachineOperand &Base = RootDef->getOperand(1);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(Base); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
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}};
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}
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return None;
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}
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/// Select a "register plus scaled unsigned 12-bit immediate" address. The
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/// "Size" argument is the size in bytes of the memory reference, which
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/// determines the scale.
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InstructionSelector::ComplexRendererFn
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AArch64InstructionSelector::selectAddrModeIndexed(MachineOperand &Root,
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unsigned Size) const {
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MachineRegisterInfo &MRI =
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Root.getParent()->getParent()->getParent()->getRegInfo();
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if (!Root.isReg())
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return None;
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MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
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if (!RootDef)
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return None;
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if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
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}};
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}
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if (isBaseWithConstantOffset(Root, MRI)) {
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MachineOperand &LHS = RootDef->getOperand(1);
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MachineOperand &RHS = RootDef->getOperand(2);
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MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg());
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MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg());
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if (LHSDef && RHSDef) {
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int64_t RHSC = (int64_t)RHSDef->getOperand(1).getCImm()->getZExtValue();
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unsigned Scale = Log2_32(Size);
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if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
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if (LHSDef->getOpcode() == TargetOpcode::G_FRAME_INDEX)
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LHSDef = MRI.getVRegDef(LHSDef->getOperand(1).getReg());
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(LHS); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC >> Scale); },
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}};
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}
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}
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}
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// Before falling back to our general case, check if the unscaled
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// instructions can handle this. If so, that's preferable.
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if (selectAddrModeUnscaled(Root, Size).hasValue())
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return None;
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
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}};
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}
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namespace llvm {
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namespace llvm {
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InstructionSelector *
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InstructionSelector *
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createAArch64InstructionSelector(const AArch64TargetMachine &TM,
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createAArch64InstructionSelector(const AArch64TargetMachine &TM,
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@ -1,5 +1,9 @@
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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# This patch temporarily causes LD1Onev1d to match instead of LDRDui on a
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# couple functions. A patch to support iPTR will follow that fixes this.
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# XFAIL: *
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--- |
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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@ -529,13 +533,13 @@ registers:
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# CHECK: body:
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# CHECK: body:
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# CHECK: %0 = COPY %x0
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# CHECK: %0 = COPY %x0
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# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
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# CHECK: %1 = LD1Onev2s %0
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# CHECK: %d0 = COPY %1
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# CHECK: %d0 = COPY %1
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body: |
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body: |
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bb.0:
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bb.0:
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liveins: %x0
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liveins: %x0
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%0(p0) = COPY %x0
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%0(p0) = COPY %x0
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%1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
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%1(<2 x s32>) = G_LOAD %0 :: (load 4 from %ir.addr)
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%d0 = COPY %1(<2 x s32>)
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%d0 = COPY %1(<2 x s32>)
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...
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...
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@ -775,8 +775,8 @@ std::set<LLTCodeGen> LLTOperandMatcher::KnownTypes;
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/// no reliable means to derive the missing type information from the pattern so
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/// no reliable means to derive the missing type information from the pattern so
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/// imported rules must test the components of a pointer separately.
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/// imported rules must test the components of a pointer separately.
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///
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///
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/// If SizeInBits is zero, then the pointer size will be obtained from the
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/// SizeInBits must be non-zero and the matched pointer must be that size.
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/// subtarget.
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/// TODO: Add support for iPTR via SizeInBits==0 and a subtarget query.
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class PointerToAnyOperandMatcher : public OperandPredicateMatcher {
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class PointerToAnyOperandMatcher : public OperandPredicateMatcher {
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protected:
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protected:
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unsigned SizeInBits;
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unsigned SizeInBits;
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@ -979,15 +979,9 @@ public:
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Error addTypeCheckPredicate(const TypeSetByHwMode &VTy,
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Error addTypeCheckPredicate(const TypeSetByHwMode &VTy,
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bool OperandIsAPointer) {
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bool OperandIsAPointer) {
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if (!VTy.isMachineValueType())
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auto OpTyOrNone = VTy.isMachineValueType()
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return failedImport("unsupported typeset");
|
? MVTToLLT(VTy.getMachineValueType().SimpleTy)
|
||||||
|
: None;
|
||||||
if (VTy.getMachineValueType() == MVT::iPTR && OperandIsAPointer) {
|
|
||||||
addPredicate<PointerToAnyOperandMatcher>(0);
|
|
||||||
return Error::success();
|
|
||||||
}
|
|
||||||
|
|
||||||
auto OpTyOrNone = MVTToLLT(VTy.getMachineValueType().SimpleTy);
|
|
||||||
if (!OpTyOrNone)
|
if (!OpTyOrNone)
|
||||||
return failedImport("unsupported type");
|
return failedImport("unsupported type");
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue