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[X86] Simplify some of the type checks in combineSubToSubus. 

If we have SSE2 we can handle any i8/i16 type and let
type legalization deal with it.

llvm-svn: 368538
This commit is contained in:
Craig Topper 2019-08-11 17:36:49 +00:00
parent 637964bfd8
commit ce6a2cf966
1 changed files with 10 additions and 5 deletions
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15
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -42860,13 +42860,15 @@ static SDValue combineSubToSubus(SDNode *N, SelectionDAG &DAG,
SDValue Op1 = N->getOperand(1);
EVT VT = N->getValueType(0);
if (!VT.isVector())
return SDValue();
// PSUBUS is supported, starting from SSE2, but truncation for v8i32
// is only worth it with SSSE3 (PSHUFB).
if (!(Subtarget.hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) &&
EVT EltVT = VT.getVectorElementType();
if (!(Subtarget.hasSSE2() && (EltVT == MVT::i8 || EltVT == MVT::i16)) &&
!(Subtarget.hasSSSE3() && (VT == MVT::v8i32 || VT == MVT::v8i64)) &&
!(Subtarget.hasAVX() && (VT == MVT::v32i8 || VT == MVT::v16i16)) &&
!(Subtarget.useBWIRegs() && (VT == MVT::v64i8 || VT == MVT::v32i16 ||
VT == MVT::v16i32 || VT == MVT::v8i64)))
!(Subtarget.useBWIRegs() && (VT == MVT::v16i32)))
return SDValue();
SDValue SubusLHS, SubusRHS;
@ -42898,9 +42900,12 @@ static SDValue combineSubToSubus(SDNode *N, SelectionDAG &DAG,
// PSUBUS doesn't support v8i32/v8i64/v16i32, but it can be enabled with
// special preprocessing in some cases.
if (VT != MVT::v8i32 && VT != MVT::v16i32 && VT != MVT::v8i64)
if (EltVT == MVT::i8 || EltVT == MVT::i16)
return DAG.getNode(ISD::USUBSAT, SDLoc(N), VT, SubusLHS, SubusRHS);
assert((VT == MVT::v8i32 || VT == MVT::v16i32 || VT == MVT::v8i64) &&
"Unexpected VT!");
// Special preprocessing case can be only applied
// if the value was zero extended from 16 bit,
// so we require first 16 bits to be zeros for 32 bit