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AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC 

The hardware will only forward EXEC_LO; the high 32 bits will be zero.

Additionally, inline constants do not work. At least,

   v_addc_u32_e64 v0, vcc, v0, v1, -1

which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.

The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine

   s_mov_b64 s[0:1], exec
   v_cndmask_b32_e64 v0, v1, v2, s[0:1]

into

   v_mov_b32 v0, v3

but it's not particularly high priority.

Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*

llvm-svn: 314522
This commit is contained in:
Nicolai Haehnle 2017-09-29 15:37:31 +00:00
parent 8fb270c691
commit ce4ddd06da
9 changed files with 61 additions and 41 deletions
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7
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -3012,15 +3012,18 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SrcCondCopy = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
.addReg(SrcCond);
BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
.addReg(Src0, 0, AMDGPU::sub0)
.addReg(Src1, 0, AMDGPU::sub0)
.addReg(SrcCond);
.addReg(SrcCondCopy);
BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
.addReg(Src0, 0, AMDGPU::sub1)
.addReg(Src1, 0, AMDGPU::sub1)
.addReg(SrcCond);
.addReg(SrcCondCopy);
BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
.addReg(DstLo)

23
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -649,15 +649,18 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
"Not a VGPR32 reg");
if (Cond.size() == 1) {
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
.add(Cond[0]);
BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
.addReg(FalseReg)
.addReg(TrueReg)
.add(Cond[0]);
.addReg(SReg);
} else if (Cond.size() == 2) {
assert(Cond[0].isImm() && "Cond[0] is not an immediate");
switch (Cond[0].getImm()) {
case SIInstrInfo::SCC_TRUE: {
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
.addImm(-1)
.addImm(0);
@ -668,7 +671,7 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
break;
}
case SIInstrInfo::SCC_FALSE: {
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg)
.addImm(0)
.addImm(-1);
@ -681,23 +684,29 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
case SIInstrInfo::VCCNZ: {
MachineOperand RegOp = Cond[1];
RegOp.setImplicit(false);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
.add(RegOp);
BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
.addReg(FalseReg)
.addReg(TrueReg)
.add(RegOp);
.addReg(SReg);
break;
}
case SIInstrInfo::VCCZ: {
MachineOperand RegOp = Cond[1];
RegOp.setImplicit(false);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
.add(RegOp);
BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
.addReg(TrueReg)
.addReg(FalseReg)
.add(RegOp);
.addReg(SReg);
break;
}
case SIInstrInfo::EXECNZ: {
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
.addImm(0);
@ -711,7 +720,7 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
break;
}
case SIInstrInfo::EXECZ: {
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
unsigned SReg = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
unsigned SReg2 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
.addImm(0);

2
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -994,7 +994,7 @@ class getVOP3SrcForVT<ValueType VT> {
VCSrc_f64,
VCSrc_b64),
!if(!eq(VT.Value, i1.Value),
SCSrc_b64,
SCSrc_i1,
!if(isFP,
!if(!eq(VT.Value, f16.Value),
VCSrc_f16,

5
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
View File

@ -121,11 +121,14 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
}
}
unsigned int TmpSrc = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass);
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::COPY), TmpSrc)
.add(Src);
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
.add(Dst)
.addImm(0)
.addImm(-1)
.add(Src);
.addReg(TmpSrc);
MI.eraseFromParent();
} else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
SrcRC == &AMDGPU::VReg_1RegClass) {

2
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -483,6 +483,8 @@ defm SSrc : RegImmOperand<"SReg", "SSrc">;
defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
def SCSrc_i1 : RegisterOperand<SReg_64_XEXEC>;
//===----------------------------------------------------------------------===//
// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
//===----------------------------------------------------------------------===//

5
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
View File

@ -1,7 +1,10 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}test1:
; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec
; CHECK: s_mov_b64 s[0:1], exec
; CHECK: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
;
; Note: The hardware doesn't implement EXEC as src2 for v_cndmask.
;
; Note: We could generate better code here if we recognized earlier that
; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,

34
llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
View File

@ -9,9 +9,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@ -42,13 +42,13 @@ registers:
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- { id: 8, class: vgpr_32 }
- { id: 9, class: sreg_64 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: vgpr_32 }
- { id: 11, class: sreg_64 }
- { id: 11, class: sreg_64_xexec }
- { id: 12, class: vgpr_32 }
- { id: 13, class: sreg_64 }
- { id: 13, class: sreg_64_xexec }
- { id: 14, class: vgpr_32 }
- { id: 15, class: sreg_64 }
- { id: 15, class: sreg_64_xexec }
body: |
bb.0:
@ -77,9 +77,9 @@ name: cluster_mov_addc
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: sreg_64 }
- { id: 2, class: sreg_64_xexec }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64 }
- { id: 4, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@ -104,12 +104,12 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
- { id: 8, class: sreg_64 }
- { id: 8, class: sreg_64_xexec }
body: |
bb.0:
%0 = V_MOV_B32_e32 0, implicit %exec
@ -130,9 +130,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@ -156,9 +156,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@ -181,7 +181,7 @@ registers:
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }
@ -210,7 +210,7 @@ registers:
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: vgpr_32 }
- { id: 4, class: sreg_64 }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: vgpr_32 }
- { id: 6, class: vgpr_32 }
- { id: 7, class: vgpr_32 }

16
llvm/test/CodeGen/AMDGPU/shrink-carry.mir
View File

@ -10,9 +10,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@ -34,9 +34,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@ -58,9 +58,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
body: |
bb.0:
@ -82,9 +82,9 @@ registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_64 }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: vgpr_32 }
- { id: 5, class: sreg_64 }
- { id: 5, class: sreg_64_xexec }
body: |
bb.0:

8
llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
View File

@ -27,7 +27,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@ -111,7 +111,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@ -195,7 +195,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }
@ -278,7 +278,7 @@ registers:
- { id: 6, class: sreg_32 }
- { id: 7, class: sreg_32 }
- { id: 8, class: sreg_32_xm0 }
- { id: 9, class: sreg_64 }
- { id: 9, class: sreg_64_xexec }
- { id: 10, class: sreg_32_xm0 }
- { id: 11, class: sreg_32_xm0 }
- { id: 12, class: sgpr_64 }