AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s". llvm-svn: 196199
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@ -779,7 +779,7 @@ def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">;
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////////////////////////////////////////////////////////////////////////////////
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// Pairwise Addition
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// With additional Qc Qs Qi QUc QUs QUi Qf Qd types.
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def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">;
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def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQlQUcQUsQUiQUlQfQd">;
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////////////////////////////////////////////////////////////////////////////////
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// Shifts by constant
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@ -951,11 +951,11 @@ def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>;
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////////////////////////////////////////////////////////////////////////////////
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// Across vectors class
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def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def VMAXV : SInst<"vmaxv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">;
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def VMINV : SInst<"vminv", "sd", "csiUcUsUiQcQsQiQUcQUsQUiQf">;
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def VADDV : SInst<"vaddv", "sd", "csiUcUsUiQcQsQiQUcQUsQUi">;
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def FMAXNMV : SInst<"vmaxnmv", "sd", "Qf">;
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def FMINNMV : SInst<"vminnmv", "sd", "Qf">;
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def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
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def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">;
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def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">;
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def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">;
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def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">;
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////////////////////////////////////////////////////////////////////////////////
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// Newly added Vector Extract for f64
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@ -1104,7 +1104,7 @@ def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">;
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////////////////////////////////////////////////////////////////////////////////
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// Scalar Reduce Pairwise Addition (Scalar and Floating Point)
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def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHd">;
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def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
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////////////////////////////////////////////////////////////////////////////////
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// Scalar Reduce Floating Point Pairwise Max/Min
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@ -1985,6 +1985,7 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
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s = "vqrshlu"; OverloadInt = true; break;
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// Scalar Reduce Pairwise Add
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case AArch64::BI__builtin_neon_vpaddd_s64:
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case AArch64::BI__builtin_neon_vpaddd_u64:
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Int = Intrinsic::aarch64_neon_vpadd; s = "vpadd";
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break;
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case AArch64::BI__builtin_neon_vpadds_f32:
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@ -2069,23 +2070,36 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
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case AArch64::BI__builtin_neon_vaddvq_s8:
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case AArch64::BI__builtin_neon_vaddvq_s16:
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case AArch64::BI__builtin_neon_vaddvq_s32:
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case AArch64::BI__builtin_neon_vaddvq_s64:
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case AArch64::BI__builtin_neon_vaddv_u8:
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case AArch64::BI__builtin_neon_vaddv_u16:
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case AArch64::BI__builtin_neon_vaddvq_u8:
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case AArch64::BI__builtin_neon_vaddvq_u16:
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case AArch64::BI__builtin_neon_vaddvq_u32:
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case AArch64::BI__builtin_neon_vaddvq_u64:
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case AArch64::BI__builtin_neon_vaddv_f32:
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case AArch64::BI__builtin_neon_vaddvq_f32:
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case AArch64::BI__builtin_neon_vaddvq_f64:
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Int = Intrinsic::aarch64_neon_vaddv;
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AcrossVec = true; ExtendEle = false; s = "vaddv"; break;
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case AArch64::BI__builtin_neon_vmaxv_f32:
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case AArch64::BI__builtin_neon_vmaxvq_f32:
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case AArch64::BI__builtin_neon_vmaxvq_f64:
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Int = Intrinsic::aarch64_neon_vmaxv;
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AcrossVec = true; ExtendEle = false; s = "vmaxv"; break;
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case AArch64::BI__builtin_neon_vminv_f32:
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case AArch64::BI__builtin_neon_vminvq_f32:
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case AArch64::BI__builtin_neon_vminvq_f64:
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Int = Intrinsic::aarch64_neon_vminv;
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AcrossVec = true; ExtendEle = false; s = "vminv"; break;
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case AArch64::BI__builtin_neon_vmaxnmv_f32:
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case AArch64::BI__builtin_neon_vmaxnmvq_f32:
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case AArch64::BI__builtin_neon_vmaxnmvq_f64:
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Int = Intrinsic::aarch64_neon_vmaxnmv;
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AcrossVec = true; ExtendEle = false; s = "vmaxnmv"; break;
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case AArch64::BI__builtin_neon_vminnmv_f32:
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case AArch64::BI__builtin_neon_vminnmvq_f32:
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case AArch64::BI__builtin_neon_vminnmvq_f64:
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Int = Intrinsic::aarch64_neon_vminnmv;
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AcrossVec = true; ExtendEle = false; s = "vminnmv"; break;
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// Scalar Integer Saturating Doubling Multiply Half High
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@ -11272,3 +11272,100 @@ int64x1_t test_vneg_s64(int64x1_t a) {
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return vneg_s64(a);
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// CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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}
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float32_t test_vaddv_f32(float32x2_t a) {
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// CHECK-LABEL: test_vaddv_f32
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return vaddv_f32(a);
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// CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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float32_t test_vaddvq_f32(float32x4_t a) {
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// CHECK-LABEL: test_vaddvq_f32
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return vaddvq_f32(a);
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// CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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// CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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float64_t test_vaddvq_f64(float64x2_t a) {
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// CHECK-LABEL: test_vaddvq_f64
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return vaddvq_f64(a);
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// CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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float32_t test_vmaxv_f32(float32x2_t a) {
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// CHECK-LABEL: test_vmaxv_f32
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return vmaxv_f32(a);
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// CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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float64_t test_vmaxvq_f64(float64x2_t a) {
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// CHECK-LABEL: test_vmaxvq_f64
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return vmaxvq_f64(a);
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// CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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float32_t test_vminv_f32(float32x2_t a) {
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// CHECK-LABEL: test_vminv_f32
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return vminv_f32(a);
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// CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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float64_t test_vminvq_f64(float64x2_t a) {
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// CHECK-LABEL: test_vminvq_f64
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return vminvq_f64(a);
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// CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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float64_t test_vmaxnmvq_f64(float64x2_t a) {
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// CHECK-LABEL: test_vmaxnmvq_f64
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return vmaxnmvq_f64(a);
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// CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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float32_t test_vmaxnmv_f32(float32x2_t a) {
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// CHECK-LABEL: test_vmaxnmv_f32
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return vmaxnmv_f32(a);
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// CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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float64_t test_vminnmvq_f64(float64x2_t a) {
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// CHECK-LABEL: test_vminnmvq_f64
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return vminnmvq_f64(a);
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// CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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float32_t test_vminnmv_f32(float32x2_t a) {
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// CHECK-LABEL: test_vminnmv_f32
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return vminnmv_f32(a);
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// CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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}
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int64x2_t test_vpaddq_s64(int64x2_t a, int64x2_t b) {
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// CHECK-LABEL: test_vpaddq_s64
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return vpaddq_s64(a, b);
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// CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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}
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uint64x2_t test_vpaddq_u64(uint64x2_t a, uint64x2_t b) {
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// CHECK-LABEL: test_vpaddq_u64
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return vpaddq_u64(a, b);
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// CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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}
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uint64_t test_vpaddd_u64(uint64x2_t a) {
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// CHECK-LABEL: test_vpaddd_u64
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return vpaddd_u64(a);
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// CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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int64_t test_vaddvq_s64(int64x2_t a) {
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// CHECK-LABEL: test_vaddvq_s64
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return vaddvq_s64(a);
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// CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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uint64_t test_vaddvq_u64(uint64x2_t a) {
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// CHECK-LABEL: test_vaddvq_u64
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return vaddvq_u64(a);
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// CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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}
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