[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
Select ballot intrinsic for GlobalISel. Differential Revision: https://reviews.llvm.org/D83214
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@ -891,6 +891,8 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
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return selectDivScale(I);
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case Intrinsic::amdgcn_icmp:
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return selectIntrinsicIcmp(I);
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case Intrinsic::amdgcn_ballot:
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return selectBallot(I);
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default:
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return selectImpl(I, *CoverageInfo);
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}
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@ -1039,6 +1041,40 @@ bool AMDGPUInstructionSelector::selectIntrinsicIcmp(MachineInstr &I) const {
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return Ret;
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}
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bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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const DebugLoc &DL = I.getDebugLoc();
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Register DstReg = I.getOperand(0).getReg();
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const unsigned Size = MRI->getType(DstReg).getSizeInBits();
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const bool Is64 = Size == 64;
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if (Size != STI.getWavefrontSize())
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return false;
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Optional<ValueAndVReg> Arg =
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getConstantVRegValWithLookThrough(I.getOperand(2).getReg(), *MRI, true);
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if (Arg.hasValue()) {
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const int64_t Value = Arg.getValue().Value;
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if (Value == 0) {
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unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
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BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg).addImm(0);
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} else if (Value == -1) { // all ones
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Register SrcReg = Is64 ? AMDGPU::EXEC : AMDGPU::EXEC_LO;
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const unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
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.addReg(SrcReg, 0, SubReg);
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} else
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return false;
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} else {
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Register SrcReg = I.getOperand(2).getReg();
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(SrcReg);
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}
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I.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
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// FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
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// SelectionDAG uses for wave32 vs wave64.
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@ -107,6 +107,7 @@ private:
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bool selectInterpP1F16(MachineInstr &MI) const;
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bool selectDivScale(MachineInstr &MI) const;
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bool selectIntrinsicIcmp(MachineInstr &MI) const;
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bool selectBallot(MachineInstr &I) const;
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bool selectG_INTRINSIC(MachineInstr &I) const;
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bool selectEndCfIntrinsic(MachineInstr &MI) const;
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@ -2989,6 +2989,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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constrainOpWithReadfirstlane(MI, MRI, 3); // Index
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return;
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}
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case Intrinsic::amdgcn_ballot:
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case Intrinsic::amdgcn_interp_p1:
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case Intrinsic::amdgcn_interp_p2:
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case Intrinsic::amdgcn_interp_mov:
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@ -4160,6 +4161,13 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[M0Idx] = AMDGPU::getValueMapping(M0Bank, 32);
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break;
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}
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case Intrinsic::amdgcn_ballot: {
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unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize);
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OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, SrcSize);
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break;
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}
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}
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break;
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}
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@ -0,0 +1,77 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -global-isel < %s | FileCheck %s
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declare i32 @llvm.amdgcn.ballot.i32(i1)
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; Test ballot(0)
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define amdgpu_cs i32 @constant_false() {
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; CHECK-LABEL: constant_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 0)
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ret i32 %ballot
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}
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; Test ballot(1)
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define amdgpu_cs i32 @constant_true() {
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; CHECK-LABEL: constant_true:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s0, exec_lo
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 1)
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ret i32 %ballot
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}
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; Test ballot of a non-comparison operation
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define amdgpu_cs i32 @non_compare(i32 %x) {
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; CHECK-LABEL: non_compare:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%trunc = trunc i32 %x to i1
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %trunc)
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ret i32 %ballot
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}
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; Test ballot of comparisons
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define amdgpu_cs i32 @compare_ints(i32 %x, i32 %y) {
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; CHECK-LABEL: compare_ints:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cmp_eq_u32_e64 s0, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp eq i32 %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define amdgpu_cs i32 @compare_int_with_constant(i32 %x) {
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; CHECK-LABEL: compare_int_with_constant:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cmp_le_i32_e64 s0, 0x63, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp sge i32 %x, 99
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define amdgpu_cs i32 @compare_floats(float %x, float %y) {
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; CHECK-LABEL: compare_floats:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = fcmp ogt float %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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@ -0,0 +1,73 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel < %s | FileCheck %s
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declare i64 @llvm.amdgcn.ballot.i64(i1)
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; Test ballot(0)
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define amdgpu_cs i64 @constant_false() {
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; CHECK-LABEL: constant_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: s_mov_b32 s1, 0
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 0)
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ret i64 %ballot
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}
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; Test ballot(1)
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define amdgpu_cs i64 @constant_true() {
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; CHECK-LABEL: constant_true:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b64 s[0:1], exec
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 1)
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ret i64 %ballot
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}
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; Test ballot of a non-comparison operation
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define amdgpu_cs i64 @non_compare(i32 %x) {
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; CHECK-LABEL: non_compare:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%trunc = trunc i32 %x to i1
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %trunc)
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ret i64 %ballot
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}
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; Test ballot of comparisons
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define amdgpu_cs i64 @compare_ints(i32 %x, i32 %y) {
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; CHECK-LABEL: compare_ints:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], v0, v1
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp eq i32 %x, %y
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
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ret i64 %ballot
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}
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define amdgpu_cs i64 @compare_int_with_constant(i32 %x) {
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; CHECK-LABEL: compare_int_with_constant:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v1, 0x63
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; CHECK-NEXT: v_cmp_ge_i32_e64 s[0:1], v0, v1
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp sge i32 %x, 99
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
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ret i64 %ballot
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}
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define amdgpu_cs i64 @compare_floats(float %x, float %y) {
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; CHECK-LABEL: compare_floats:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_cmp_gt_f32_e64 s[0:1], v0, v1
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = fcmp ogt float %x, %y
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
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ret i64 %ballot
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}
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@ -5,44 +5,37 @@ declare i32 @llvm.amdgcn.ballot.i32(i1)
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; Test ballot(0)
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define i32 @test0() {
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; CHECK-LABEL: test0:
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define amdgpu_cs i32 @constant_false() {
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; CHECK-LABEL: constant_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 0)
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ret i32 %ballot
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}
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; Test ballot(1)
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define i32 @test1() {
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; CHECK-LABEL: test1:
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define amdgpu_cs i32 @constant_true() {
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; CHECK-LABEL: constant_true:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, exec_lo
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; CHECK-NEXT: s_mov_b32 s0, exec_lo
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 1)
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ret i32 %ballot
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}
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; Test ballot of a non-comparison operation
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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define amdgpu_cs i32 @non_compare(i32 %x) {
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; CHECK-LABEL: non_compare:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_cmp_ne_u32_e64 s4, 0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%trunc = trunc i32 %x to i1
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %trunc)
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ret i32 %ballot
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@ -50,43 +43,34 @@ define i32 @test2(i32 %x) {
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; Test ballot of comparisons
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define i32 @test3(i32 %x, i32 %y) {
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; CHECK-LABEL: test3:
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define amdgpu_cs i32 @compare_ints(i32 %x, i32 %y) {
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; CHECK-LABEL: compare_ints:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_eq_u32_e64 s4, v0, v1
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; CHECK-NEXT: v_cmp_eq_u32_e64 s0, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp eq i32 %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: test4:
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define amdgpu_cs i32 @compare_int_with_constant(i32 %x) {
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; CHECK-LABEL: compare_int_with_constant:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_lt_i32_e64 s4, 0x62, v0
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; CHECK-NEXT: v_cmp_lt_i32_e64 s0, 0x62, v0
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = icmp sge i32 %x, 99
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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}
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define i32 @test5(float %x, float %y) {
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; CHECK-LABEL: test5:
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define amdgpu_cs i32 @compare_floats(float %x, float %y) {
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; CHECK-LABEL: compare_floats:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: v_cmp_gt_f32_e64 s4, v0, v1
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; CHECK-NEXT: v_cmp_gt_f32_e64 s0, v0, v1
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; CHECK-NEXT: ; implicit-def: $vcc_hi
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: ; return to shader part epilog
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%cmp = fcmp ogt float %x, %y
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%ballot = call i32 @llvm.amdgcn.ballot.i32(i1 %cmp)
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ret i32 %ballot
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@ -5,41 +5,36 @@ declare i64 @llvm.amdgcn.ballot.i64(i1)
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; Test ballot(0)
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define i64 @test0() {
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; CHECK-LABEL: test0:
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define amdgpu_cs i64 @constant_false() {
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; CHECK-LABEL: constant_false:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: s_mov_b32 s0, 0
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; CHECK-NEXT: s_mov_b32 s1, 0
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 0)
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ret i64 %ballot
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}
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; Test ballot(1)
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define i64 @test1() {
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; CHECK-LABEL: test1:
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define amdgpu_cs i64 @constant_true() {
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; CHECK-LABEL: constant_true:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, exec_lo
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; CHECK-NEXT: v_mov_b32_e32 v1, exec_hi
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: s_mov_b32 s0, exec_lo
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; CHECK-NEXT: s_mov_b32 s1, exec_hi
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; CHECK-NEXT: ; return to shader part epilog
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%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 1)
|
||||
ret i64 %ballot
|
||||
}
|
||||
|
||||
; Test ballot of a non-comparison operation
|
||||
|
||||
define i64 @test2(i32 %x) {
|
||||
; CHECK-LABEL: test2:
|
||||
define amdgpu_cs i64 @non_compare(i32 %x) {
|
||||
; CHECK-LABEL: non_compare:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
||||
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
%trunc = trunc i32 %x to i1
|
||||
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %trunc)
|
||||
ret i64 %ballot
|
||||
|
@ -47,41 +42,32 @@ define i64 @test2(i32 %x) {
|
|||
|
||||
; Test ballot of comparisons
|
||||
|
||||
define i64 @test3(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: test3:
|
||||
define amdgpu_cs i64 @compare_ints(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: compare_ints:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
||||
; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], v0, v1
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
%cmp = icmp eq i32 %x, %y
|
||||
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
|
||||
ret i64 %ballot
|
||||
}
|
||||
|
||||
define i64 @test4(i32 %x) {
|
||||
; CHECK-LABEL: test4:
|
||||
define amdgpu_cs i64 @compare_int_with_constant(i32 %x) {
|
||||
; CHECK-LABEL: compare_int_with_constant:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: s_movk_i32 s4, 0x62
|
||||
; CHECK-NEXT: v_cmp_lt_i32_e64 s[4:5], s4, v0
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
||||
; CHECK-NEXT: s_movk_i32 s0, 0x62
|
||||
; CHECK-NEXT: v_cmp_lt_i32_e64 s[0:1], s0, v0
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
%cmp = icmp sge i32 %x, 99
|
||||
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
|
||||
ret i64 %ballot
|
||||
}
|
||||
|
||||
define i64 @test5(float %x, float %y) {
|
||||
; CHECK-LABEL: test5:
|
||||
define amdgpu_cs i64 @compare_floats(float %x, float %y) {
|
||||
; CHECK-LABEL: compare_floats:
|
||||
; CHECK: ; %bb.0:
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: v_cmp_gt_f32_e64 s[4:5], v0, v1
|
||||
; CHECK-NEXT: v_mov_b32_e32 v0, s4
|
||||
; CHECK-NEXT: v_mov_b32_e32 v1, s5
|
||||
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
||||
; CHECK-NEXT: v_cmp_gt_f32_e64 s[0:1], v0, v1
|
||||
; CHECK-NEXT: ; return to shader part epilog
|
||||
%cmp = fcmp ogt float %x, %y
|
||||
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
|
||||
ret i64 %ballot
|
||||
|
|
Loading…
Reference in New Issue