[LLDB][MIPS] Software single stepping

Patch by Jaydeep Patil

Reviewers: clayborg, jasonmolenda
Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits.
Differential Revision: http://reviews.llvm.org/D9519

llvm-svn: 236696

lldb/source/API/SystemInitializerFull.cpp

@@ -25,7 +25,6 @@
 #include "Plugins/Disassembler/llvm/DisassemblerLLVMC.h"
 #include "Plugins/DynamicLoader/Static/DynamicLoaderStatic.h"
 #include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
-#include "Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h"
 #include "Plugins/InstrumentationRuntime/AddressSanitizer/AddressSanitizerRuntime.h"
 #include "Plugins/JITLoader/GDB/JITLoaderGDB.h"
 #include "Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.h"
@@ -255,7 +254,6 @@ SystemInitializerFull::Initialize()
     UnwindAssemblyInstEmulation::Initialize();
     UnwindAssembly_x86::Initialize();
     EmulateInstructionARM64::Initialize();
-    EmulateInstructionMIPS64::Initialize();
     SymbolFileDWARFDebugMap::Initialize();
     ItaniumABILanguageRuntime::Initialize();
     AppleObjCRuntimeV2::Initialize();
@@ -360,7 +358,6 @@ SystemInitializerFull::Terminate()
     UnwindAssembly_x86::Terminate();
     UnwindAssemblyInstEmulation::Terminate();
     EmulateInstructionARM64::Terminate();
-    EmulateInstructionMIPS64::Terminate();
     SymbolFileDWARFDebugMap::Terminate();
     ItaniumABILanguageRuntime::Terminate();
     AppleObjCRuntimeV2::Terminate();

lldb/source/Initialization/SystemInitializerCommon.cpp

@@ -18,6 +18,7 @@
 #include "Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.h"
 #include "Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.h"
 #include "Plugins/Instruction/ARM/EmulateInstructionARM.h"
+#include "Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h"
 #include "Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.h"
 #include "Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.h"
 #include "Plugins/ObjectFile/ELF/ObjectFileELF.h"
@@ -112,6 +113,7 @@ SystemInitializerCommon::Initialize()
     platform_android::PlatformAndroid::Initialize();
 
     EmulateInstructionARM::Initialize();
+    EmulateInstructionMIPS64::Initialize();
 
     //----------------------------------------------------------------------
     // Apple/Darwin hosted plugins
@@ -161,6 +163,7 @@ SystemInitializerCommon::Terminate()
     PlatformiOSSimulator::Terminate();
 
     EmulateInstructionARM::Terminate();
+    EmulateInstructionMIPS64::Terminate();
 
 #if defined(__APPLE__)
     DynamicLoaderDarwinKernel::Terminate();

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

@@ -48,6 +48,14 @@ using namespace lldb_private;
 //
 //----------------------------------------------------------------------
 
+extern "C" {
+    void LLVMInitializeMipsTargetInfo ();
+    void LLVMInitializeMipsTarget ();
+    void LLVMInitializeMipsAsmPrinter ();
+    void LLVMInitializeMipsTargetMC ();
+    void LLVMInitializeMipsDisassembler ();
+}
+
 EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch) :
     EmulateInstruction (arch)
 {
@@ -55,8 +63,63 @@ EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec
     std::string Error;
     llvm::Triple triple = arch.GetTriple();
     const llvm::Target *target = llvm::TargetRegistry::lookupTarget (triple.getTriple(), Error);
+
+    /*
+     * If we fail to get the target then we haven't registered it. The SystemInitializerCommon 
+     * does not initialize targets, MCs and disassemblers. However we need the MCDisassembler 
+     * to decode the instructions so that the decoding complexity stays with LLVM. 
+     * Initialize the MIPS targets and disassemblers.
+    */
+    if (!target)
+    {
+        LLVMInitializeMipsTargetInfo ();
+        LLVMInitializeMipsTarget ();
+        LLVMInitializeMipsAsmPrinter ();
+        LLVMInitializeMipsTargetMC ();
+        LLVMInitializeMipsDisassembler ();
+        target = llvm::TargetRegistry::lookupTarget (triple.getTriple(), Error);
+    }
+
     assert (target);
 
+    llvm::StringRef cpu;
+
+    switch (arch.GetCore())
+    {
+        case ArchSpec::eCore_mips32:
+        case ArchSpec::eCore_mips32el:
+            cpu = "mips32"; break;
+        case ArchSpec::eCore_mips32r2:
+        case ArchSpec::eCore_mips32r2el:
+            cpu = "mips32r2"; break;
+        case ArchSpec::eCore_mips32r3:
+        case ArchSpec::eCore_mips32r3el:
+            cpu = "mips32r3"; break;
+        case ArchSpec::eCore_mips32r5:
+        case ArchSpec::eCore_mips32r5el:
+            cpu = "mips32r5"; break;
+        case ArchSpec::eCore_mips32r6:
+        case ArchSpec::eCore_mips32r6el:
+            cpu = "mips32r6"; break;
+        case ArchSpec::eCore_mips64:
+        case ArchSpec::eCore_mips64el:
+            cpu = "mips64"; break;
+        case ArchSpec::eCore_mips64r2:
+        case ArchSpec::eCore_mips64r2el:
+            cpu = "mips64r2"; break;
+        case ArchSpec::eCore_mips64r3:
+        case ArchSpec::eCore_mips64r3el:
+            cpu = "mips64r3"; break;
+        case ArchSpec::eCore_mips64r5:
+        case ArchSpec::eCore_mips64r5el:
+            cpu = "mips64r5"; break;
+        case ArchSpec::eCore_mips64r6:
+        case ArchSpec::eCore_mips64r6el:
+            cpu = "mips64r6"; break;
+        default:
+            cpu = "generic"; break;
+    }
+
     m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
     assert (m_reg_info.get());
 
@@ -64,7 +127,7 @@ EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec
     assert (m_insn_info.get());
 
     m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
-    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), "", ""));
+    m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
     assert (m_asm_info.get() && m_subtype_info.get());
 
     m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
@@ -207,7 +270,6 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
             case LLDB_REGNUM_GENERIC_FP:    reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips64; break;
             case LLDB_REGNUM_GENERIC_RA:    reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips64; break;
             case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips64; break;
-                 return true;
             default:
                 return false;
         }

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

@@ -51,9 +51,9 @@ public:
         {
             case lldb_private::eInstructionTypeAny:
             case lldb_private::eInstructionTypePrologueEpilogue:
+            case lldb_private::eInstructionTypePCModifying:
                 return true;
 
-            case lldb_private::eInstructionTypePCModifying:
             case lldb_private::eInstructionTypeAll:
                 return false;
         }

lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp

@@ -2885,10 +2885,8 @@ ReadRegisterCallback (EmulateInstruction *instruction,
 
     Error error = emulator_baton->m_reg_context->ReadRegister(full_reg_info, reg_value);
     if (error.Success())
-    {
-        emulator_baton->m_register_values[reg_info->kinds[eRegisterKindDWARF]] = reg_value;
         return true;
-    }
+
     return false;
 }
 
@@ -2995,6 +2993,9 @@ NativeProcessLinux::SetupSoftwareSingleStepping(NativeThreadProtocolSP thread_sp
             error = SetSoftwareBreakpoint(next_pc, 4);
         }
     }
+    else if (m_arch.GetMachine() == llvm::Triple::mips64
+            || m_arch.GetMachine() == llvm::Triple::mips64el)
+        error = SetSoftwareBreakpoint(next_pc, 4);
     else
     {
         // No size hint is given for the next breakpoint
@@ -3012,7 +3013,10 @@ NativeProcessLinux::SetupSoftwareSingleStepping(NativeThreadProtocolSP thread_sp
 bool
 NativeProcessLinux::SupportHardwareSingleStepping() const
 {
-    return m_arch.GetMachine() != llvm::Triple::arm;
+    if (m_arch.GetMachine() == llvm::Triple::arm
+        || m_arch.GetMachine() == llvm::Triple::mips64 || m_arch.GetMachine() == llvm::Triple::mips64el)
+        return false;
+    return true;
 }
 
 Error