Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
llvm-svn: 147366
This commit is contained in:
parent
c0f9bcb5d5
commit
cd93de93fa
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@ -426,10 +426,9 @@ namespace X86II {
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/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
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/// this flag to indicate that the encoder should do the wacky 3DNow! thing.
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Has3DNow0F0FOpcode = 1U << 7,
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Has3DNow0F0FOpcode = 1U << 7,
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/// XOP_W - Same bit as VEX_W. Used to indicate swapping of
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/// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
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/// operand 3 and 4 to be encoded in ModRM or I8IMM. This is used
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/// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
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/// for FMA4 and XOP instructions.
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MemOp4 = 1U << 8,
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XOP_W = 1U << 8,
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/// XOP - Opcode prefix used by XOP instructions.
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/// XOP - Opcode prefix used by XOP instructions.
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XOP = 1U << 9
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XOP = 1U << 9
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@ -503,11 +502,11 @@ namespace X86II {
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return 0;
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return 0;
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case X86II::MRMSrcMem: {
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case X86II::MRMSrcMem: {
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasXOP_W = (TSFlags >> X86II::VEXShift) & X86II::XOP_W;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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unsigned FirstMemOp = 1;
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unsigned FirstMemOp = 1;
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if (HasVEX_4V)
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if (HasVEX_4V)
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++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
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++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
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if (HasXOP_W)
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if (HasMemOp4)
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++FirstMemOp;// Skip the register source (which is encoded in I8IMM).
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++FirstMemOp;// Skip the register source (which is encoded in I8IMM).
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// FIXME: Maybe lea should have its own form? This is a horrible hack.
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// FIXME: Maybe lea should have its own form? This is a horrible hack.
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@ -431,10 +431,6 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// opcode extension, or ignored, depending on the opcode byte)
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// opcode extension, or ignored, depending on the opcode byte)
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unsigned char VEX_W = 0;
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unsigned char VEX_W = 0;
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// XOP_W: opcode specific, same bit as VEX_W, but used to
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// swap operand 3 and 4 for FMA4 and XOP instructions
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unsigned char XOP_W = 0;
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// XOP: Use XOP prefix byte 0x8f instead of VEX.
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// XOP: Use XOP prefix byte 0x8f instead of VEX.
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unsigned char XOP = 0;
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unsigned char XOP = 0;
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@ -477,9 +473,6 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
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VEX_W = 1;
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VEX_W = 1;
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if ((TSFlags >> X86II::VEXShift) & X86II::XOP_W)
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XOP_W = 1;
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if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
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if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
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XOP = 1;
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XOP = 1;
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@ -669,7 +662,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 3 byte VEX prefix
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// 3 byte VEX prefix
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EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
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EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
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EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
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EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
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EmitByte(LastByte | ((VEX_W | XOP_W) << 7), CurByte, OS);
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EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
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}
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}
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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@ -929,8 +922,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// It uses the VEX.VVVV field?
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// It uses the VEX.VVVV field?
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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bool HasXOP_W = (TSFlags >> X86II::VEXShift) & X86II::XOP_W;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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unsigned XOP_W_I8IMMOperand = 2;
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const unsigned MemOp4_I8IMMOperand = 2;
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// Determine where the memory operand starts, if present.
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// Determine where the memory operand starts, if present.
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int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
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int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
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@ -1003,14 +996,14 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
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if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
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SrcRegNum++;
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SrcRegNum++;
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if(HasXOP_W) // Skip 2nd src (which is encoded in I8IMM)
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if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
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SrcRegNum++;
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SrcRegNum++;
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EmitRegModRMByte(MI.getOperand(SrcRegNum),
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EmitRegModRMByte(MI.getOperand(SrcRegNum),
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GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
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GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
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// 2 operands skipped with HasXOP_W, comensate accordingly
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// 2 operands skipped with HasMemOp4, comensate accordingly
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CurOp = HasXOP_W ? SrcRegNum : SrcRegNum + 1;
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CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
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if (HasVEX_4VOp3)
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if (HasVEX_4VOp3)
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++CurOp;
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++CurOp;
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break;
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break;
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@ -1022,7 +1015,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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++AddrOperands;
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++AddrOperands;
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++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
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++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
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}
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}
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if(HasXOP_W) // Skip second register source (encoded in I8IMM)
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if(HasMemOp4) // Skip second register source (encoded in I8IMM)
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++FirstMemOp;
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++FirstMemOp;
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EmitByte(BaseOpcode, CurByte, OS);
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EmitByte(BaseOpcode, CurByte, OS);
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@ -1113,7 +1106,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// The last source register of a 4 operand instruction in AVX is encoded
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// The last source register of a 4 operand instruction in AVX is encoded
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// in bits[7:4] of a immediate byte.
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// in bits[7:4] of a immediate byte.
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
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const MCOperand &MO = MI.getOperand(HasXOP_W ? XOP_W_I8IMMOperand
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const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
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: CurOp);
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: CurOp);
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CurOp++;
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CurOp++;
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bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
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bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg());
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@ -105,13 +105,13 @@ multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, XOP_W;
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(Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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(ins VR128:$src1, memop:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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@ -128,13 +128,13 @@ multiclass fma4p<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
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(Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
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(ld_frag128 addr:$src3)))]>, XOP_W;
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(ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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@ -146,13 +146,13 @@ multiclass fma4p<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst,
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[(set VR256:$dst,
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(Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, XOP_W;
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(Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
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def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
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[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
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(ld_frag256 addr:$src3)))]>, XOP_W;
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(ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
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def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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@ -120,7 +120,7 @@ class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
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class VEX_L { bit hasVEX_L = 1; }
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class VEX_L { bit hasVEX_L = 1; }
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class VEX_LIG { bit ignoresVEX_L = 1; }
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class VEX_LIG { bit ignoresVEX_L = 1; }
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class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
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class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
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class XOP_W { bit hasXOP_WPrefix = 1; }
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class MemOp4 { bit hasMemOp4Prefix = 1; }
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class XOP { bit hasXOP_Prefix = 1; }
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class XOP { bit hasXOP_Prefix = 1; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr, Domain d = GenericDomain>
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string AsmStr, Domain d = GenericDomain>
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@ -161,7 +161,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
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bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
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bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
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bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
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bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
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bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
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bit hasXOP_WPrefix = 0; // Same bit as VEX_W, but used for swapping operands
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bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
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bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
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bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
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// TSFlags layout should be kept in sync with X86InstrInfo.h.
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// TSFlags layout should be kept in sync with X86InstrInfo.h.
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@ -184,7 +184,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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let TSFlags{38} = hasVEX_L;
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let TSFlags{38} = hasVEX_L;
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let TSFlags{39} = ignoresVEX_L;
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let TSFlags{39} = ignoresVEX_L;
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let TSFlags{40} = has3DNow0F0FOpcode;
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let TSFlags{40} = has3DNow0F0FOpcode;
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let TSFlags{41} = hasXOP_WPrefix;
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let TSFlags{41} = hasMemOp4Prefix;
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let TSFlags{42} = hasXOP_Prefix;
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let TSFlags{42} = hasXOP_Prefix;
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}
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}
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@ -169,7 +169,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr> {
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM, XOP_W;
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[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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(ins VR128:$src1, f128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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@ -192,7 +192,7 @@ multiclass xop4op256<bits<8> opc, string OpcodeStr> {
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, VEX_4V, VEX_I8IMM, XOP_W;
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[]>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
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def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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(ins VR256:$src1, f256mem:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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@ -214,7 +214,7 @@ multiclass xop5op<bits<8> opc, string OpcodeStr> {
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(ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
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[]>, XOP_W;
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[]>, VEX_W, MemOp4;
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def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
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||||||
(ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
|
(ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
|
||||||
!strconcat(OpcodeStr,
|
!strconcat(OpcodeStr,
|
||||||
|
@ -229,7 +229,7 @@ multiclass xop5op<bits<8> opc, string OpcodeStr> {
|
||||||
(ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
|
(ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
|
||||||
!strconcat(OpcodeStr,
|
!strconcat(OpcodeStr,
|
||||||
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
||||||
[]>, XOP_W;
|
[]>, VEX_W, MemOp4;
|
||||||
def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
|
def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
|
||||||
(ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
|
(ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
|
||||||
!strconcat(OpcodeStr,
|
!strconcat(OpcodeStr,
|
||||||
|
|
Loading…
Reference in New Issue