From cd8d97393267dbc90c23f233dee52b67caffe653 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas Date: Sun, 29 Nov 2015 10:53:28 +0000 Subject: [PATCH] ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply Add/Subtract. Add missing tests that accidentally were not committed in rL254250. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254251 --- .../CodeGen/aarch64-v8.1a-neon-intrinsics.c | 128 ++++++++++++++++++ .../test/CodeGen/arm-v8.1a-neon-intrinsics.c | 121 +++++++++++++++++ 2 files changed, 249 insertions(+) create mode 100644 clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c create mode 100644 clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c diff --git a/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c b/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c new file mode 100644 index 000000000000..078b454b3973 --- /dev/null +++ b/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c @@ -0,0 +1,128 @@ +// REQUIRES: aarch64-registered-target + +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ +// RUN: -target-feature +v8.1a -O3 -S -o - %s \ +// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 + + #include + +// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s16 +int16x4_t test_vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) { +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7] + return vqrdmlah_laneq_s16(a, b, v, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s32 +int32x2_t test_vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) { +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3] + return vqrdmlah_laneq_s32(a, b, v, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s16 +int16x8_t test_vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) { +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7] + return vqrdmlahq_laneq_s16(a, b, v, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s32 +int32x4_t test_vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) { +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3] + return vqrdmlahq_laneq_s32(a, b, v, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahh_s16 +int16_t test_vqrdmlahh_s16(int16_t a, int16_t b, int16_t c) { +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}} + return vqrdmlahh_s16(a, b, c); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahs_s32 +int32_t test_vqrdmlahs_s32(int32_t a, int32_t b, int32_t c) { +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + return vqrdmlahs_s32(a, b, c); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahh_lane_s16 +int16_t test_vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t c) { +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3] + return vqrdmlahh_lane_s16(a, b, c, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahs_lane_s32 +int32_t test_vqrdmlahs_lane_s32(int32_t a, int32_t b, int32x2_t c) { +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1] + return vqrdmlahs_lane_s32(a, b, c, 1); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahh_laneq_s16 +int16_t test_vqrdmlahh_laneq_s16(int16_t a, int16_t b, int16x8_t c) { +// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7] + return vqrdmlahh_laneq_s16(a, b, c, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlahs_laneq_s32 +int32_t test_vqrdmlahs_laneq_s32(int32_t a, int32_t b, int32x4_t c) { +// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3] + return vqrdmlahs_laneq_s32(a, b, c, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s16 +int16x4_t test_vqrdmlsh_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) { +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7] + return vqrdmlsh_laneq_s16(a, b, v, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s32 +int32x2_t test_vqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) { +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3] + return vqrdmlsh_laneq_s32(a, b, v, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s16 +int16x8_t test_vqrdmlshq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) { +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7] + return vqrdmlshq_laneq_s16(a, b, v, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s32 +int32x4_t test_vqrdmlshq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) { +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3] + return vqrdmlshq_laneq_s32(a, b, v, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshh_s16 +int16_t test_vqrdmlshh_s16(int16_t a, int16_t b, int16_t c) { +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}} + return vqrdmlshh_s16(a, b, c); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshs_s32 +int32_t test_vqrdmlshs_s32(int32_t a, int32_t b, int32_t c) { +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + return vqrdmlshs_s32(a, b, c); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshh_lane_s16 +int16_t test_vqrdmlshh_lane_s16(int16_t a, int16_t b, int16x4_t c) { +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3] + return vqrdmlshh_lane_s16(a, b, c, 3); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshs_lane_s32 +int32_t test_vqrdmlshs_lane_s32(int32_t a, int32_t b, int32x2_t c) { +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1] + return vqrdmlshs_lane_s32(a, b, c, 1); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshh_laneq_s16 +int16_t test_vqrdmlshh_laneq_s16(int16_t a, int16_t b, int16x8_t c) { +// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7] + return vqrdmlshh_laneq_s16(a, b, c, 7); +} + +// CHECK-AARCH64-LABEL: test_vqrdmlshs_laneq_s32 +int32_t test_vqrdmlshs_laneq_s32(int32_t a, int32_t b, int32x4_t c) { +// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3] + return vqrdmlshs_laneq_s32(a, b, c, 3); +} + diff --git a/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c b/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c new file mode 100644 index 000000000000..f826e3166a54 --- /dev/null +++ b/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c @@ -0,0 +1,121 @@ +// RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \ +// RUN: -O3 -S -o - %s \ +// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ +// RUN: -target-feature +v8.1a -O3 -S -o - %s \ +// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 + +#include + +// CHECK-LABEL: test_vqrdmlah_s16 +int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h + return vqrdmlah_s16(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlah_s32 +int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + return vqrdmlah_s32(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlahq_s16 +int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) { +// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h + return vqrdmlahq_s16(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlahq_s32 +int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) { +// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s + return vqrdmlahq_s32(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlah_lane_s16 +int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3] +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3] + return vqrdmlah_lane_s16(a, b, c, 3); +} + +// CHECK-LABEL: test_vqrdmlah_lane_s32 +int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1] +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1] + return vqrdmlah_lane_s32(a, b, c, 1); +} + +// CHECK-LABEL: test_vqrdmlahq_lane_s16 +int16x8_t test_vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3] +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3] + return vqrdmlahq_lane_s16(a, b, c, 3); +} + +// CHECK-LABEL: test_vqrdmlahq_lane_s32 +int32x4_t test_vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1] +// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1] + return vqrdmlahq_lane_s32(a, b, c, 1); +} + +// CHECK-LABEL: test_vqrdmlsh_s16 +int16x4_t test_vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h + return vqrdmlsh_s16(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlsh_s32 +int32x2_t test_vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s + return vqrdmlsh_s32(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlshq_s16 +int16x8_t test_vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c) { +// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h + return vqrdmlshq_s16(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlshq_s32 +int32x4_t test_vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c) { +// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s + return vqrdmlshq_s32(a, b, c); +} + +// CHECK-LABEL: test_vqrdmlsh_lane_s16 +int16x4_t test_vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3] +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3] + return vqrdmlsh_lane_s16(a, b, c, 3); +} + +// CHECK-LABEL: test_vqrdmlsh_lane_s32 +int32x2_t test_vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1] +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1] + return vqrdmlsh_lane_s32(a, b, c, 1); +} + +// CHECK-LABEL: test_vqrdmlshq_lane_s16 +int16x8_t test_vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) { +// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3] +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3] + return vqrdmlshq_lane_s16(a, b, c, 3); +} + +// CHECK-LABEL: test_vqrdmlshq_lane_s32 +int32x4_t test_vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) { +// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1] +// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1] + return vqrdmlshq_lane_s32(a, b, c, 1); +} +