Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case. llvm-svn: 119749
This commit is contained in:
parent
2acd1621f4
commit
cd68095650
|
@ -4985,7 +4985,8 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
|
|||
EVT VT = N->getValueType(0);
|
||||
|
||||
// Nothing to be done for scalar shifts.
|
||||
if (! VT.isVector())
|
||||
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
||||
if (!VT.isVector() || !TLI.isTypeLegal(VT))
|
||||
return SDValue();
|
||||
|
||||
assert(ST->hasNEON() && "unexpected vector shift");
|
||||
|
|
|
@ -0,0 +1,8 @@
|
|||
; RUN: llc < %s -march=arm -mattr=+neon
|
||||
define void @lshrIllegalType(<8 x i32>* %A) nounwind {
|
||||
%tmp1 = load <8 x i32>* %A
|
||||
%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
|
||||
store <8 x i32> %tmp2, <8 x i32>* %A
|
||||
ret void
|
||||
}
|
||||
|
Loading…
Reference in New Issue