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ARM two-operand aliases for VRHADD instructions. 

rdar://11252521

llvm-svn: 154832
This commit is contained in:
Jim Grosbach 2012-04-16 17:14:11 +00:00
parent 5b1910a741
commit cd1c000a9f
2 changed files with 59 additions and 0 deletions
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32
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -6951,6 +6951,38 @@ def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
(VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
// Two-operand variants for VRHADD.
// Signed.
def : NEONInstAlias<"vrhadd${p}.s8 $Vdn, $Rm",
(VRHADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.s16 $Vdn, $Rm",
(VRHADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.s32 $Vdn, $Rm",
(VRHADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.s8 $Vdn, $Rm",
(VRHADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.s16 $Vdn, $Rm",
(VRHADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.s32 $Vdn, $Rm",
(VRHADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
// Unsigned.
def : NEONInstAlias<"vrhadd${p}.u8 $Vdn, $Rm",
(VRHADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.u16 $Vdn, $Rm",
(VRHADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.u32 $Vdn, $Rm",
(VRHADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.u8 $Vdn, $Rm",
(VRHADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.u16 $Vdn, $Rm",
(VRHADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
def : NEONInstAlias<"vrhadd${p}.u32 $Vdn, $Rm",
(VRHADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
// VSWP allows, but does not require, a type suffix.
defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
(VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;

27
llvm/test/MC/ARM/neon-add-encoding.s
View File

@ -77,6 +77,19 @@
vrhadd.u8 q8, q8, q9
vrhadd.u16 q8, q8, q9
vrhadd.u32 q8, q8, q9
@ Two-operand forms.
vrhadd.s8 d16, d17
vrhadd.s16 d16, d17
vrhadd.s32 d16, d17
vrhadd.u8 d16, d17
vrhadd.u16 d16, d17
vrhadd.u32 d16, d17
vrhadd.s8 q8, q9
vrhadd.s16 q8, q9
vrhadd.s32 q8, q9
vrhadd.u8 q8, q9
vrhadd.u16 q8, q9
vrhadd.u32 q8, q9
@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2]
@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2]
@ -91,6 +104,20 @@
@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3]
@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3]
@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf2]
@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf2]
@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf2]
@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xf3]
@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xf3]
@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xf3]
@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf2]
@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf2]
@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf2]
@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xf3]
@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xf3]
@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xf3]
vqadd.s8 d16, d16, d17
vqadd.s16 d16, d16, d17
vqadd.s32 d16, d16, d17