[X86][SSE] Support for MOVMSK signbit extraction instructions
Add support for lowering with the MOVMSK instruction to extract vector element signbits to a GPR. This is an early step towards more optimal handling of vector comparison results. Differential Revision: http://reviews.llvm.org/D18741 llvm-svn: 265266
This commit is contained in:
Simon Pilgrim
parent
f87e550e89
commit
cd0dfc93eb
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@ -21888,6 +21888,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::AND: return "X86ISD::AND";
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case X86ISD::BEXTR: return "X86ISD::BEXTR";
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case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
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case X86ISD::MOVMSK: return "X86ISD::MOVMSK";
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case X86ISD::PTEST: return "X86ISD::PTEST";
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case X86ISD::TESTP: return "X86ISD::TESTP";
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case X86ISD::TESTM: return "X86ISD::TESTM";
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@ -24018,36 +24019,12 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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case X86ISD::SETCC:
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KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
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break;
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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unsigned NumLoBits = 0;
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switch (IntId) {
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default: break;
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case Intrinsic::x86_sse_movmsk_ps:
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case Intrinsic::x86_avx_movmsk_ps_256:
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case Intrinsic::x86_sse2_movmsk_pd:
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case Intrinsic::x86_avx_movmsk_pd_256:
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case Intrinsic::x86_mmx_pmovmskb:
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case Intrinsic::x86_sse2_pmovmskb_128:
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case Intrinsic::x86_avx2_pmovmskb: {
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// High bits of movmskp{s|d}, pmovmskb are known zero.
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switch (IntId) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
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case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
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case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
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case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
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case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
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case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
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case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
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}
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case X86ISD::MOVMSK: {
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unsigned NumLoBits = Op.getOperand(0).getValueType().getVectorNumElements();
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KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
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break;
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}
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}
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break;
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}
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}
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}
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unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
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@ -352,6 +352,9 @@ namespace llvm {
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// X86-specific multiply by immediate.
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MUL_IMM,
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// Vector sign bit extraction.
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MOVMSK,
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// Vector bitwise comparisons.
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PTEST,
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@ -276,6 +276,9 @@ def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
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def X86testm : SDNode<"X86ISD::TESTM", SDTX86Testm, [SDNPCommutative]>;
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def X86testnm : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>;
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def X86movmsk : SDNode<"X86ISD::MOVMSK",
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SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
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def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
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def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
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@ -2765,25 +2765,23 @@ let Predicates = [HasAVX1Only] in {
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//===----------------------------------------------------------------------===//
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/// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
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multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
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Domain d> {
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multiclass sse12_extr_sign_mask<RegisterClass RC, ValueType vt,
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string asm, Domain d> {
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def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
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[(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
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[(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], IIC_SSE_MOVMSK, d>,
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Sched<[WriteVecLogic]>;
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}
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let Predicates = [HasAVX] in {
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defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
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"movmskps", SSEPackedSingle>, PS, VEX;
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defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
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"movmskpd", SSEPackedDouble>, PD, VEX;
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defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
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"movmskps", SSEPackedSingle>, PS,
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VEX, VEX_L;
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defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
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"movmskpd", SSEPackedDouble>, PD,
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VEX, VEX_L;
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defm VMOVMSKPS : sse12_extr_sign_mask<VR128, v4f32, "movmskps",
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SSEPackedSingle>, PS, VEX;
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defm VMOVMSKPD : sse12_extr_sign_mask<VR128, v2f64, "movmskpd",
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SSEPackedDouble>, PD, VEX;
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defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, v8f32, "movmskps",
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SSEPackedSingle>, PS, VEX, VEX_L;
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defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, v4f64, "movmskpd",
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SSEPackedDouble>, PD, VEX, VEX_L;
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def : Pat<(i32 (X86fgetsign FR32:$src)),
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(VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
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@ -2797,9 +2795,9 @@ let Predicates = [HasAVX] in {
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(VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
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}
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defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
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defm MOVMSKPS : sse12_extr_sign_mask<VR128, v4f32, "movmskps",
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SSEPackedSingle>, PS;
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defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
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defm MOVMSKPD : sse12_extr_sign_mask<VR128, v2f64, "movmskpd",
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SSEPackedDouble>, PD;
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def : Pat<(i32 (X86fgetsign FR32:$src)),
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@ -4665,20 +4663,20 @@ let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
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def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
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(ins VR128:$src),
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"pmovmskb\t{$src, $dst|$dst, $src}",
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[(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
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[(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))],
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IIC_SSE_MOVMSK>, VEX;
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let Predicates = [HasAVX2] in {
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def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
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(ins VR256:$src),
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"pmovmskb\t{$src, $dst|$dst, $src}",
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[(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
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[(set GR32orGR64:$dst, (X86movmsk (v32i8 VR256:$src)))]>,
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VEX, VEX_L;
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}
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def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
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"pmovmskb\t{$src, $dst|$dst, $src}",
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[(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
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[(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))],
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IIC_SSE_MOVMSK>;
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} // ExeDomain = SSEPackedInt
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@ -321,6 +321,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx_max_ps_256, INTR_TYPE_2OP, X86ISD::FMAX, 0),
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X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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X86_INTRINSIC_DATA(avx_movmsk_pd_256, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(avx_movmsk_ps_256, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(avx_rcp_ps_256, INTR_TYPE_1OP, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx_rsqrt_ps_256, INTR_TYPE_1OP, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
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@ -354,6 +356,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(avx2_pminu_d, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(avx2_pminu_w, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(avx2_pmovmskb, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(avx2_pmovsxbd, INTR_TYPE_1OP, X86ISD::VSEXT, 0),
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X86_INTRINSIC_DATA(avx2_pmovsxbq, INTR_TYPE_1OP, X86ISD::VSEXT, 0),
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X86_INTRINSIC_DATA(avx2_pmovsxbw, INTR_TYPE_1OP, X86ISD::VSEXT, 0),
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@ -2184,6 +2187,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
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X86_INTRINSIC_DATA(sse_max_ps, INTR_TYPE_2OP, X86ISD::FMAX, 0),
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X86_INTRINSIC_DATA(sse_min_ps, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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X86_INTRINSIC_DATA(sse_movmsk_ps, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(sse_rcp_ps, INTR_TYPE_1OP, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(sse_rsqrt_ps, INTR_TYPE_1OP, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
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@ -2201,6 +2205,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
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X86_INTRINSIC_DATA(sse2_max_pd, INTR_TYPE_2OP, X86ISD::FMAX, 0),
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X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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X86_INTRINSIC_DATA(sse2_movmsk_pd, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(sse2_packssdw_128, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
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X86_INTRINSIC_DATA(sse2_packsswb_128, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
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X86_INTRINSIC_DATA(sse2_packuswb_128, INTR_TYPE_2OP, X86ISD::PACKUS, 0),
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@ -2210,6 +2215,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0),
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X86_INTRINSIC_DATA(sse2_pmins_w, INTR_TYPE_2OP, ISD::SMIN, 0),
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X86_INTRINSIC_DATA(sse2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0),
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X86_INTRINSIC_DATA(sse2_pmovmskb_128, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
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X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
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X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
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X86_INTRINSIC_DATA(sse2_pmulu_dq, INTR_TYPE_2OP, X86ISD::PMULUDQ, 0),
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