Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.
llvm-svn: 93028
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@ -7831,14 +7831,16 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
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.addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
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unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
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unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
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// The subsequent operations should be using the destination registers of
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//the PHI instructions.
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if (invSrc) {
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
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t1 = F->getRegInfo().createVirtualRegister(RC);
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t2 = F->getRegInfo().createVirtualRegister(RC);
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
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} else {
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tt1 = t1;
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tt2 = t2;
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t1 = dest1Oper.getReg();
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t2 = dest2Oper.getReg();
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}
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int valArgIndx = lastAddrIndx + 1;
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@ -7852,7 +7854,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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else
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MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
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if (regOpcL != X86::MOV32rr)
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MIB.addReg(tt1);
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MIB.addReg(t1);
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(*MIB).addOperand(*argOpers[valArgIndx]);
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assert(argOpers[valArgIndx + 1]->isReg() ==
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argOpers[valArgIndx]->isReg());
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@ -7863,7 +7865,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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else
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MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
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if (regOpcH != X86::MOV32rr)
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MIB.addReg(tt2);
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MIB.addReg(t2);
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(*MIB).addOperand(*argOpers[valArgIndx + 1]);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
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@ -0,0 +1,29 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
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; rdar://r7512579
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; PHI defs in the atomic loop should be used by the add / adc
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; instructions. They should not be dead.
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define void @t(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK: t:
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; CHECK: movl $1
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; CHECK: movl (%ebp), %eax
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; CHECK: movl 4(%ebp), %edx
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; CHECK: LBB1_1:
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; CHECK-NOT: movl $1
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; CHECK-NOT: movl $0
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; CHECK: addl
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; CHECK: adcl
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; CHECK: lock
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; CHECK: cmpxchg8b
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; CHECK: jne
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tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
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%0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
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tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
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ret void
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}
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declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
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declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind
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