[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment
Differential Revision: https://reviews.llvm.org/D39657 llvm-svn: 317479
This commit is contained in:
Yaxun Liu
parent
6720a089fd
commit
cc56a8b108
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@ -245,6 +245,10 @@ GCNMinRegSchedRegistry("gcn-minreg",
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static StringRef computeDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::r600) {
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// 32-bit pointers.
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if (TT.getEnvironmentName() == "amdgiz" ||
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TT.getEnvironmentName() == "amdgizcl")
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
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return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
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"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
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}
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@ -1,5 +1,6 @@
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
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; RUN: opt -S -mtriple=r600-unknown-unknown -mcpu=redwood -amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
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; RUN: opt -S -mtriple=r600-unknown-unknown-amdgiz -mcpu=redwood -amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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@ -18,19 +19,19 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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define amdgpu_kernel void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
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entry:
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%stack = alloca [5 x i32], align 4
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0
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store i32 4, i32* %arrayidx1, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1
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store i32 5, i32* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0
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%2 = load i32, i32* %arrayidx10, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1
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%3 = load i32, i32* %arrayidx12
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %3, i32 addrspace(1)* %arrayidx13
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ret void
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@ -49,20 +50,20 @@ entry:
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define amdgpu_kernel void @multiple_structs(i32 addrspace(1)* %out) #0 {
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entry:
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%a = alloca %struct.point
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%b = alloca %struct.point
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%a.x.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 0
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%a.y.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 1
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%b.x.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 0
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%b.y.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 1
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store i32 0, i32* %a.x.ptr
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store i32 1, i32* %a.y.ptr
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store i32 2, i32* %b.x.ptr
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store i32 3, i32* %b.y.ptr
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%a.indirect.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 0
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%b.indirect.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 0
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%a.indirect = load i32, i32* %a.indirect.ptr
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%b.indirect = load i32, i32* %b.indirect.ptr
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%a = alloca %struct.point, addrspace(5)
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%b = alloca %struct.point, addrspace(5)
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%a.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
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%a.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 1
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%b.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
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%b.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %a.x.ptr
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store i32 1, i32 addrspace(5)* %a.y.ptr
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store i32 2, i32 addrspace(5)* %b.x.ptr
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store i32 3, i32 addrspace(5)* %b.y.ptr
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%a.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
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%b.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
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%a.indirect = load i32, i32 addrspace(5)* %a.indirect.ptr
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%b.indirect = load i32, i32 addrspace(5)* %b.indirect.ptr
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%0 = add i32 %a.indirect, %b.indirect
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store i32 %0, i32 addrspace(1)* %out
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ret void
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@ -77,32 +78,32 @@ entry:
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define amdgpu_kernel void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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entry:
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%prv_array_const = alloca [2 x i32]
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%prv_array = alloca [2 x i32]
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%prv_array_const = alloca [2 x i32], addrspace(5)
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%prv_array = alloca [2 x i32], addrspace(5)
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%a = load i32, i32 addrspace(1)* %in
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%b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%b = load i32, i32 addrspace(1)* %b_src_ptr
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%a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0
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store i32 %a, i32* %a_dst_ptr
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%b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1
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store i32 %b, i32* %b_dst_ptr
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%a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
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store i32 %a, i32 addrspace(5)* %a_dst_ptr
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%b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 1
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store i32 %b, i32 addrspace(5)* %b_dst_ptr
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br label %for.body
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for.body:
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%inc = phi i32 [0, %entry], [%count, %for.body]
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%x_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0
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%x = load i32, i32* %x_ptr
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%y_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0
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%y = load i32, i32* %y_ptr
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%x_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
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%x = load i32, i32 addrspace(5)* %x_ptr
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%y_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
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%y = load i32, i32 addrspace(5)* %y_ptr
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%xy = add i32 %x, %y
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store i32 %xy, i32* %y_ptr
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store i32 %xy, i32 addrspace(5)* %y_ptr
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%count = add i32 %inc, 1
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%done = icmp eq i32 %count, 4095
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br i1 %done, label %for.end, label %for.body
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for.end:
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%value_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0
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%value = load i32, i32* %value_ptr
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%value_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
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%value = load i32, i32 addrspace(5)* %value_ptr
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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@ -112,13 +113,13 @@ for.end:
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; R600: MOVA_INT
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define amdgpu_kernel void @short_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = alloca [2 x i16]
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%1 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 1
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store i16 0, i16* %1
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store i16 1, i16* %2
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%3 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 %index
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%4 = load i16, i16* %3
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%0 = alloca [2 x i16], addrspace(5)
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%1 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 1
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store i16 0, i16 addrspace(5)* %1
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store i16 1, i16 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 %index
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%4 = load i16, i16 addrspace(5)* %3
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%5 = sext i16 %4 to i32
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store i32 %5, i32 addrspace(1)* %out
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ret void
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@ -129,13 +130,13 @@ entry:
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; R600: MOVA_INT
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define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = alloca [2 x i8]
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%1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1
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store i8 0, i8* %1
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store i8 1, i8* %2
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%3 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 %index
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%4 = load i8, i8* %3
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%0 = alloca [2 x i8], addrspace(5)
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%1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %1
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store i8 1, i8 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 %index
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%4 = load i8, i8 addrspace(5)* %3
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%5 = sext i8 %4 to i32
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store i32 %5, i32 addrspace(1)* %out
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ret void
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@ -150,13 +151,13 @@ entry:
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; R600-NOT: MOV * TO.X
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define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%0 = alloca [2 x i32]
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%1 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 1
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store i32 0, i32* %1
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store i32 1, i32* %2
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%3 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 %in
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%4 = load i32, i32* %3
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%0 = alloca [2 x i32], addrspace(5)
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%1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %1
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store i32 1, i32 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
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%4 = load i32, i32 addrspace(5)* %3
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%5 = call i32 @llvm.r600.read.tidig.x()
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%6 = add i32 %4, %5
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store i32 %6, i32 addrspace(1)* %out
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@ -171,22 +172,22 @@ entry:
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; R600-NOT: [[CHAN]]+
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define amdgpu_kernel void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%0 = alloca [3 x i8], align 1
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%1 = alloca [2 x i8], align 1
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%2 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 0
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%3 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 1
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%4 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 2
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%5 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 0
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%6 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 1
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store i8 0, i8* %2
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store i8 1, i8* %3
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store i8 2, i8* %4
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store i8 1, i8* %5
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store i8 0, i8* %6
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%7 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 %in
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%8 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 %in
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%9 = load i8, i8* %7
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%10 = load i8, i8* %8
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%0 = alloca [3 x i8], align 1, addrspace(5)
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%1 = alloca [2 x i8], align 1, addrspace(5)
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%2 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 0
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%3 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 1
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%4 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 2
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%5 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 0
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%6 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %2
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store i8 1, i8 addrspace(5)* %3
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store i8 2, i8 addrspace(5)* %4
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store i8 1, i8 addrspace(5)* %5
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store i8 0, i8 addrspace(5)* %6
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%7 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 %in
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%8 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 %in
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%9 = load i8, i8 addrspace(5)* %7
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%10 = load i8, i8 addrspace(5)* %8
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%11 = add i8 %9, %10
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%12 = sext i8 %11 to i32
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store i32 %12, i32 addrspace(1)* %out
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@ -195,13 +196,13 @@ entry:
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define amdgpu_kernel void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x i8]]
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%gep0 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1
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store i8 0, i8* %gep0
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store i8 1, i8* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index
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%load = load i8, i8* %gep2
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%alloca = alloca [2 x [2 x i8]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %gep0
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store i8 1, i8 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
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%load = load i8, i8 addrspace(5)* %gep2
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%sext = sext i8 %load to i32
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store i32 %sext, i32 addrspace(1)* %out
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ret void
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@ -209,26 +210,26 @@ entry:
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define amdgpu_kernel void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x i32]]
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%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1
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store i32 0, i32* %gep0
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store i32 1, i32* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index
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%load = load i32, i32* %gep2
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%alloca = alloca [2 x [2 x i32]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
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%load = load i32, i32 addrspace(5)* %gep2
|
||||
store i32 %load, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 {
|
||||
entry:
|
||||
%alloca = alloca [2 x [2 x i64]]
|
||||
%gep0 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0
|
||||
%gep1 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1
|
||||
store i64 0, i64* %gep0
|
||||
store i64 1, i64* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index
|
||||
%load = load i64, i64* %gep2
|
||||
%alloca = alloca [2 x [2 x i64]], addrspace(5)
|
||||
%gep0 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
|
||||
%gep1 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
|
||||
store i64 0, i64 addrspace(5)* %gep0
|
||||
store i64 1, i64 addrspace(5)* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
|
||||
%load = load i64, i64 addrspace(5)* %gep2
|
||||
store i64 %load, i64 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
|
@ -237,40 +238,40 @@ entry:
|
|||
|
||||
define amdgpu_kernel void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
|
||||
entry:
|
||||
%alloca = alloca [2 x [2 x %struct.pair32]]
|
||||
%gep0 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1
|
||||
%gep1 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1
|
||||
store i32 0, i32* %gep0
|
||||
store i32 1, i32* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0
|
||||
%load = load i32, i32* %gep2
|
||||
%alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5)
|
||||
%gep0 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0, i32 1
|
||||
%gep1 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1, i32 1
|
||||
store i32 0, i32 addrspace(5)* %gep0
|
||||
store i32 1, i32 addrspace(5)* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index, i32 0
|
||||
%load = load i32, i32 addrspace(5)* %gep2
|
||||
store i32 %load, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 {
|
||||
entry:
|
||||
%alloca = alloca [2 x %struct.pair32]
|
||||
%gep0 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1
|
||||
%gep1 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0
|
||||
store i32 0, i32* %gep0
|
||||
store i32 1, i32* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0
|
||||
%load = load i32, i32* %gep2
|
||||
%alloca = alloca [2 x %struct.pair32], addrspace(5)
|
||||
%gep0 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 0, i32 1
|
||||
%gep1 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 1, i32 0
|
||||
store i32 0, i32 addrspace(5)* %gep0
|
||||
store i32 1, i32 addrspace(5)* %gep1
|
||||
%gep2 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 %index, i32 0
|
||||
%load = load i32, i32 addrspace(5)* %gep2
|
||||
store i32 %load, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind {
|
||||
entry:
|
||||
%tmp = alloca [2 x i32]
|
||||
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0
|
||||
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1
|
||||
store i32 0, i32* %tmp1
|
||||
store i32 1, i32* %tmp2
|
||||
%tmp = alloca [2 x i32], addrspace(5)
|
||||
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
|
||||
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
|
||||
store i32 0, i32 addrspace(5)* %tmp1
|
||||
store i32 1, i32 addrspace(5)* %tmp2
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
%sel = select i1 %cmp, i32* %tmp1, i32* %tmp2
|
||||
%load = load i32, i32* %sel
|
||||
%sel = select i1 %cmp, i32 addrspace(5)* %tmp1, i32 addrspace(5)* %tmp2
|
||||
%load = load i32, i32 addrspace(5)* %sel
|
||||
store i32 %load, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
|
@ -283,14 +284,14 @@ entry:
|
|||
; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
|
||||
; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ;
|
||||
define amdgpu_kernel void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
|
||||
%alloca = alloca [16 x i32]
|
||||
%tmp0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a
|
||||
store i32 5, i32* %tmp0
|
||||
%tmp1 = ptrtoint [16 x i32]* %alloca to i32
|
||||
%alloca = alloca [16 x i32], addrspace(5)
|
||||
%tmp0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
|
||||
store i32 5, i32 addrspace(5)* %tmp0
|
||||
%tmp1 = ptrtoint [16 x i32] addrspace(5)* %alloca to i32
|
||||
%tmp2 = add i32 %tmp1, 5
|
||||
%tmp3 = inttoptr i32 %tmp2 to i32*
|
||||
%tmp4 = getelementptr inbounds i32, i32* %tmp3, i32 %b
|
||||
%tmp5 = load i32, i32* %tmp4
|
||||
%tmp3 = inttoptr i32 %tmp2 to i32 addrspace(5)*
|
||||
%tmp4 = getelementptr inbounds i32, i32 addrspace(5)* %tmp3, i32 %b
|
||||
%tmp5 = load i32, i32 addrspace(5)* %tmp4
|
||||
store i32 %tmp5, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
; RUN: llc -march=amdgcn -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
|
||||
; RUN: llc -march=r600 -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s
|
||||
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
|
||||
; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s
|
||||
target datalayout = "A5"
|
||||
|
||||
; Should not crash when the processor is not recognized and the
|
||||
; wavefront size feature not set.
|
||||
|
|
@ -14,7 +15,7 @@
|
|||
|
||||
; R600: MOV
|
||||
define amdgpu_kernel void @foo() {
|
||||
%alloca = alloca i32, align 4
|
||||
store volatile i32 0, i32* %alloca
|
||||
%alloca = alloca i32, align 4, addrspace(5)
|
||||
store volatile i32 0, i32 addrspace(5)* %alloca
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue