Fix PR10656. It's only profitable to use 128-bit inserts and extracts
when AVX mode is one. Otherwise is just more work for the type legalizer. llvm-svn: 137661
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@ -11737,7 +11737,8 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
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/// PerformShuffleCombine - Performs several different shuffle combines.
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/// PerformShuffleCombine - Performs several different shuffle combines.
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static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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DebugLoc dl = N->getDebugLoc();
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DebugLoc dl = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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@ -11746,8 +11747,9 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
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if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
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return SDValue();
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return SDValue();
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// Only handle pure VECTOR_SHUFFLE nodes.
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// Combine 256-bit vector shuffles. This is only profitable when in AVX mode
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if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE)
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if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
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N->getOpcode() == ISD::VECTOR_SHUFFLE)
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return PerformShuffleCombine256(N, DAG, DCI);
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return PerformShuffleCombine256(N, DAG, DCI);
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// Only handle 128 wide vector from here on.
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// Only handle 128 wide vector from here on.
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@ -13220,7 +13222,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILPDY:
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case X86ISD::VPERMILPDY:
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case X86ISD::VPERM2F128:
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case X86ISD::VPERM2F128:
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
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}
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}
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return SDValue();
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return SDValue();
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s
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; CHECK-NOT: vunpck
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; CHECK-NOT: vunpck
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; CHECK: vinsertf128 $1
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; CHECK: vinsertf128 $1
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@ -16,3 +17,22 @@ entry:
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ret <4 x double> %shuffle
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ret <4 x double> %shuffle
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}
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}
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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; Just check that no crash happens
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; CHECK-SSE: _insert_crash
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define void @insert_crash() nounwind {
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allocas:
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%v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>
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%vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
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%ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
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%ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0
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%double2float = fptrunc double %ret.i1.i.i464 to float
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%smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3
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%blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>
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store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4
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ret void
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}
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