Add some hooks for selecting memory addresses.
llvm-svn: 26347
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@ -49,11 +49,28 @@ public:
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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return true;
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}
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protected:
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/// Pick a safe ordering and emit instructions for each target node in the
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/// graph.
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void ScheduleAndEmitDAG(SelectionDAG &DAG);
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops,
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SelectionDAG &DAG);
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private:
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SDOperand CopyValueToVirtualRegister(SelectionDAGLowering &SDL,
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Value *V, unsigned Reg);
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