[AMDGPU] Simplify setcc (sext from i1 b), -1|0, cc
Depending on the compare code that can be either an argument of sext or negate of it. This helps to avoid v_cndmask_b64 instruction for sext. A reversed value can be further simplified and folded into its parent comparison if possible. Differential Revision: https://reviews.llvm.org/D34545 llvm-svn: 306446
This commit is contained in:
Stanislav Mekhanoshin
parent
3f91be52c3
commit
c9bd53ab59
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@ -5135,6 +5135,35 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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EVT VT = LHS.getValueType();
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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auto CRHS = dyn_cast<ConstantSDNode>(RHS);
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if (!CRHS) {
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CRHS = dyn_cast<ConstantSDNode>(LHS);
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if (CRHS) {
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std::swap(LHS, RHS);
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CC = getSetCCSwappedOperands(CC);
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}
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}
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if (CRHS && VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
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isBoolSGPR(LHS.getOperand(0))) {
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// setcc (sext from i1 cc), -1, ne|sgt|ult) => not cc => xor cc, -1
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// setcc (sext from i1 cc), -1, eq|sle|uge) => cc
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// setcc (sext from i1 cc), 0, eq|sge|ule) => not cc => xor cc, -1
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// setcc (sext from i1 cc), 0, ne|ugt|slt) => cc
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if ((CRHS->isAllOnesValue() &&
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(CC == ISD::SETNE || CC == ISD::SETGT || CC == ISD::SETULT)) ||
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(CRHS->isNullValue() &&
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(CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
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return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
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DAG.getConstant(-1, SL, MVT::i1));
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if ((CRHS->isAllOnesValue() &&
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(CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
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(CRHS->isNullValue() &&
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(CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
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return LHS.getOperand(0);
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}
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if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
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VT != MVT::f16))
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@ -5142,7 +5171,6 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
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// Match isinf pattern
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// (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
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const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
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if (!CRHS)
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@ -0,0 +1,292 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}setcc_sgt_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sgt_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sgt i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sgt_true_sext_swap:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sgt_true_sext_swap(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp slt i32 -1, %ext
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ne_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ne_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ne i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ult_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ult_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ult i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_eq_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_eq_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp eq i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sle_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sle_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sle i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_uge_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_uge_true_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp uge i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_eq_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_eq_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp eq i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sge_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sge_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sge i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ule_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ule_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ule i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ne_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ne_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ne i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ugt_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ugt_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ugt i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_slt_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_slt_false_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp slt i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, i32 addrspace(1)* %arg, align 4
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br label %endif
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endif:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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attributes #0 = { nounwind readnone speculatable }
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