parent
d82c183d70
commit
c9ad7c9fcb
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@ -72,7 +72,7 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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return NULL;
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}
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bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
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bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) {
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if (!RC) {
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return false;
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}
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@ -47,7 +47,7 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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/// \returns true if this class contains only SGPR registers
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bool isSGPRClass(const TargetRegisterClass *RC) const;
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static bool isSGPRClass(const TargetRegisterClass *RC);
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};
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} // End namespace llvm
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