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Don't set neverHasSideEffects on x86's divide instructions, since 

they trap on divide-by-zero, and this side effect is otherwise
unmodeled.

llvm-svn: 59551
This commit is contained in:
Dan Gohman 2008-11-18 21:29:14 +00:00
parent 6e58726416
commit c8d2b0135a
2 changed files with 1 additions and 3 deletions
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2
llvm/lib/Target/X86/X86Instr64bit.td
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@ -474,7 +474,6 @@ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
} // Defs = [EFLAGS] } // Defs = [EFLAGS]
// Unsigned division / remainder // Unsigned division / remainder
let neverHasSideEffects = 1 in {
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in { let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
"div{q}\t$src", []>; "div{q}\t$src", []>;
@ -488,7 +487,6 @@ def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64]
"idiv{q}\t$src", []>; "idiv{q}\t$src", []>;
} }
} }
}
// Unary instructions // Unary instructions
let Defs = [EFLAGS], CodeSize = 2 in { let Defs = [EFLAGS], CodeSize = 2 in {

2
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -747,6 +747,7 @@ let Defs = [EAX,EDX], Uses = [EAX] in
def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
"imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32] "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
} }
} // neverHasSideEffects
// unsigned division/remainder // unsigned division/remainder
let Defs = [AL,AH,EFLAGS], Uses = [AX] in let Defs = [AL,AH,EFLAGS], Uses = [AX] in
@ -791,7 +792,6 @@ let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
"idiv{l}\t$src", []>; "idiv{l}\t$src", []>;
} }
} // neverHasSideEffects
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Two address Instructions. // Two address Instructions.