diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d32a9f052d4a..0607797b7133 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7511,7 +7511,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
     case 'l':   // INDEX_REGS
       if (VT == MVT::i64 && Subtarget->is64Bit())
         return std::make_pair(0U, X86::GR64RegisterClass);
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::i64)
         return std::make_pair(0U, X86::GR32RegisterClass);
       else if (VT == MVT::i16)
         return std::make_pair(0U, X86::GR16RegisterClass);
diff --git a/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
new file mode 100644
index 000000000000..eb2ec3760b9e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86
+; RUN: llvm-as < %s | llc -march=x86-64
+
+define void @test(i64 %x) nounwind {
+entry:
+	tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+	ret void
+}
+