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Fix global live range splitting regmask accuracy. 

Pretend that regmask interference ends at the 'dead' slot, even when
there is other interference ending at the 'reg' slot of the same
instruction.

llvm-svn: 150531
This commit is contained in:
Jakob Stoklund Olesen 2012-02-14 23:53:23 +00:00
parent b0c0d340f8
commit c4cf13f791
1 changed files with 2 additions and 1 deletions
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3
llvm/lib/CodeGen/InterferenceCache.cpp
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@ -185,7 +185,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
// Also check for register mask interference.
SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
for (unsigned i = RegMaskSlots.size(); i && RegMaskSlots[i-1] > Limit; --i)
for (unsigned i = RegMaskSlots.size();
i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
// Register mask i-1 clobbers PhysReg after the LIU interference.
// Model the regmask clobber as a dead def.