[X86] Relax an assertion when legalizing vector types.
WidenVSELECTAndMask can fold (and it folds in this case) so we get a BUILD_VECTOR of constants as mask. convertMask() seems to work fine when the input is a vector of constants, and we still need to call it to extend/add elements at the end. but the current code just asserts on anything but a SETCC or AND/OR/XOR of 2xSETCC. This change was discussed briefly with Simon Pilgrim, who also suggests we might consider dropping this assertion in the future. Fixes PR33715. llvm-svn: 307508
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@ -2977,7 +2977,11 @@ SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
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// Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
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unsigned InMaskOpc = InMask->getOpcode();
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// FIXME: This code seems to be too restrictive, we might consider
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// generalizing it or dropping it.
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assert((InMaskOpc == ISD::SETCC ||
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ISD::isBuildVectorOfConstantSDNodes(InMask.getNode()) ||
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(isLogicalMaskOp(InMaskOpc) &&
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isSETCCorConvertedSETCC(InMask->getOperand(0)) &&
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isSETCCorConvertedSETCC(InMask->getOperand(1)))) &&
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@ -0,0 +1,16 @@
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; Make sure we don't crash with a build vector of integer constants.
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; RUN: llc %s -o /dev/null
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i32 @patatino() {
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%tmp = insertelement <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>, i32 1, i32 2
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%tmp1 = insertelement <4 x i32> %tmp, i32 1, i32 3
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%tmp2 = icmp ne <4 x i32> %tmp1, zeroinitializer
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%tmp3 = icmp slt <4 x i32> %tmp1, <i32 4, i32 4, i32 4, i32 4>
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%tmp4 = or <4 x i1> %tmp2, %tmp3
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%tmp5 = select <4 x i1> %tmp4, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 4, i32 4, i32 4>
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%tmp6 = extractelement <4 x i32> %tmp5, i32 0
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ret i32 %tmp6
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}
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