Added MachineInstrInfo class and moved instruction-related members there.
Added several fields to MachineInstrDescriptor (and renamed it from MachineInstrInfo. Latency fields are to support scheduling. llvm-svn: 308
This commit is contained in:
Vikram S. Adve
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bff682dfac
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c429691751
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@ -18,6 +18,7 @@
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class Type;
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class StructType;
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struct MachineInstrDescriptor;
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//---------------------------------------------------------------------------
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@ -28,22 +29,100 @@ typedef int MachineOpCode;
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typedef int OpCodeMask;
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class MachineInstrInfo.
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//
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extern const MachineInstrDescriptor* TargetInstrDescriptors;
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//---------------------------------------------------------------------------
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// struct MachineInstrInfo:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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struct MachineInstrInfo {
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//
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//---------------------------------------------------------------------------
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const unsigned int M_NOP_FLAG = 1;
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const unsigned int M_BRANCH_FLAG = 1 << 1;
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const unsigned int M_CALL_FLAG = 1 << 2;
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const unsigned int M_RET_FLAG = 1 << 3;
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const unsigned int M_ARITH_FLAG = 1 << 4;
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const unsigned int M_CC_FLAG = 1 << 6;
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const unsigned int M_LOGICAL_FLAG = 1 << 6;
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const unsigned int M_INT_FLAG = 1 << 7;
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const unsigned int M_FLOAT_FLAG = 1 << 8;
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const unsigned int M_CONDL_FLAG = 1 << 9;
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const unsigned int M_LOAD_FLAG = 1 << 10;
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const unsigned int M_PREFETCH_FLAG = 1 << 11;
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const unsigned int M_STORE_FLAG = 1 << 12;
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struct MachineInstrDescriptor {
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string opCodeString; // Assembly language mnemonic for the opcode.
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unsigned int numOperands; // Number of arguments for the instruction.
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int resultPos; // Position of the result; -1 if no result
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unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is the IMMED field sign-extended? If so,
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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unsigned int numDelaySlots; // Number of delay slots after instruction
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unsigned int latency; // Latency in machine cycles
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unsigned int iclass; // Flags identifying instruction class
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};
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class MachineInstrInfo : public NonCopyableV {
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protected:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned int descSize; // number of entries in the array
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public:
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/*ctor*/ MachineInstrInfo(const MachineInstrDescriptor* _desc,
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unsigned int _descSize);
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/*dtor*/ virtual ~MachineInstrInfo();
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const MachineInstrDescriptor& getDescriptor (MachineOpCode opCode) const {
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assert(opCode < (int) descSize);
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return desc[opCode]; }
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virtual bool isBranch (MachineOpCode opCode) const {
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return desc[opCode].iclass & M_BRANCH_FLAG;}
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virtual bool isLoad (MachineOpCode opCode) const {
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return desc[opCode].iclass & M_LOAD_FLAG
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|| desc[opCode].iclass & M_PREFETCH_FLAG;}
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virtual bool isStore (MachineOpCode opCode) const {
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return desc[opCode].iclass & M_STORE_FLAG;}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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// Default to true since most instructions on many architectures allow this.
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//
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true; }
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true; }
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//
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency (MachineOpCode opCode) const {
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return desc[opCode].latency; }
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virtual int maxLatency (MachineOpCode opCode) const {
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return desc[opCode].latency; }
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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bool constantFitsInImmedField (int64_t intValue) const;
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virtual bool constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const;
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// Return the largest +ve constant that can be held in the IMMMED field
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// of this machine instruction.
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@ -51,22 +130,18 @@ struct MachineInstrInfo {
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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inline uint64_t maxImmedConstant(bool& isSignExtended) const {
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isSignExtended = immedIsSignExtended;
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return maxImmedConst; }
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool& isSignExtended) const {
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isSignExtended = desc[opCode].immedIsSignExtended;
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return desc[opCode].maxImmedConst; }
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};
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// Global variable holding an array of the above structures.
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// This needs to be defined separately for each target machine.
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//
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extern const MachineInstrInfo* TargetMachineInstrInfo;
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//---------------------------------------------------------------------------
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// class TargetMachine
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//
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// Purpose:
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// Machine description.
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// Primary interface to machine description for the target machine.
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//
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//---------------------------------------------------------------------------
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@ -82,21 +157,31 @@ public:
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int minMemOpWordSize;
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int maxAtomicMemOpWordSize;
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// Description of machine instructions (array indexed by machine opcode)
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const MachineInstrInfo* machineInstrInfo;
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// Register information. This needs to be reorganized into a single class.
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int zeroRegNum; // register that gives 0 if any (-1 if none)
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public:
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/*ctor*/ TargetMachine () {}
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/*dtor*/ virtual ~TargetMachine () {}
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/*ctor*/ TargetMachine (MachineInstrInfo* mii)
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: machineInstrInfo(mii) {}
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/*dtor*/ virtual ~TargetMachine () {}
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const MachineInstrInfo& getInstrInfo () const { return *machineInstrInfo; }
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virtual unsigned int findOptimalStorageSize (const Type* ty) const;
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virtual unsigned int* findOptimalMemberOffsets(const StructType* stype)const;
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protected:
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// Description of machine instructions
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// Protect so that subclass can control alloc/dealloc
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MachineInstrInfo* machineInstrInfo;
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private:
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/*ctor*/ TargetMachine (); // disable
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};
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//**************************************************************************/
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#endif
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@ -15,18 +15,36 @@
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#include "llvm/CodeGen/TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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//************************ Exported Constants ******************************/
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// External object describing the machine instructions
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// Initialized only when the TargetMachine class is created
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// and reset when that class is destroyed.
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//
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const MachineInstrDescriptor* TargetInstrDescriptors = NULL;
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//************************ Class Implementations **************************/
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//---------------------------------------------------------------------------
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// function TargetMachine::findOptimalMemberOffsets
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// class TargetMachine
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//
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// Purpose:
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// Compute optimal offsets for the members of a structure.
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// Returns a vector of unsigned ints, one per member.
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// Caller is responsible for freeing the vector.
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// Machine description.
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//
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//---------------------------------------------------------------------------
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// function TargetMachine::findOptimalStorageSize
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//
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// Purpose:
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// Compute optimal storage size for a structure, based on
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// the optimal member offsets.
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// This default implementation assumes that all sub-word data items use
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// space equal to optSizeForSubWordData, and all other primitive data
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// items use space according to the type.
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//
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unsigned int
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TargetMachine::findOptimalStorageSize(const Type* ty) const
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{
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@ -87,6 +105,14 @@ TargetMachine::findOptimalStorageSize(const Type* ty) const
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}
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}
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// function TargetMachine::findOptimalMemberOffsets
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//
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// Purpose:
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// Compute optimal offsets for the members of a structure.
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// Returns a vector of unsigned ints, one per member.
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// Caller is responsible for freeing the vector.
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unsigned int*
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TargetMachine::findOptimalMemberOffsets(const StructType* stype) const
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{
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@ -102,4 +128,46 @@ TargetMachine::findOptimalMemberOffsets(const StructType* stype) const
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return offsetVec;
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}
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//---------------------------------------------------------------------------
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//---------------------------------------------------------------------------
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/*ctor*/
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MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
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unsigned int _descSize)
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: desc(_desc), descSize(_descSize)
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{
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assert(TargetInstrDescriptors == NULL && desc != NULL);
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TargetInstrDescriptors = desc; // initialize global variable
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}
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/*dtor*/
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MachineInstrInfo::~MachineInstrInfo()
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{
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TargetInstrDescriptors = NULL; // reset global variable
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}
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bool
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MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const
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{
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// First, check if opCode has an immed field.
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bool isSignExtended;
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uint64_t maxImmedValue = this->maxImmedConstant(opCode, isSignExtended);
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if (maxImmedValue != 0)
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{
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// Now check if the constant fits
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if (intValue <= (int64_t) maxImmedValue &&
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intValue >= -((int64_t) maxImmedValue+1))
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return true;
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}
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return false;
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}
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//---------------------------------------------------------------------------
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